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參數(shù)資料
| 型號： | AD5532ABCZ-2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 32CH BIPO 74-CSPBGA |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設(shè)置時間： | 30µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 34 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 623mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 74-LBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 74-CSPBGA（12x12） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | 45k |
| 配用： | EVAL-AD5532HSEBZ-ND - BOARD EVAL FOR AD5532HS EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532 |
AD5532
Rev. D | Page 15 of 20
TRACK FUNCTION (ISHA MODE)
Typically in ISHA mode of operation TRACK is held high and
the channel begins to acquire when it is addressed. However, if
TRACK is low when the channel is addressed, VIN is switched to
the output buffer and an acquisition on the channel does not
occur until a rising edge of TRACK. At this stage, the BUSY pin
goes low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and VIN
is free to change again without affecting this output value.
This is useful in an application where the user wants to ramp up
does not need to be acquired continuously while it is ramping
up. TRACK can be kept low and only when VOUT has reached its
desired voltage is TRACK brought high. At this stage, the
acquisition of VIN begins.
In the example shown, a desired voltage is required on the
output of the pin driver. This voltage is represented by one input
to a comparator. The microcontroller/microprocessor ramps up
the input voltage on VIN through a DAC. TRACK is kept low
while the voltage on VIN ramps up so that VIN is not continually
acquired. When the desired voltage is reached on the output of
the pin driver, the comparator output switches. The μC/μP then
knows what code is required to be input to obtain the desired
voltage at the DUT. The TRACK input is now brought high and
the part begins to acquire VIN. At this stage BUSY goes low until
VIN has been acquired. The output buffer is then switched from
VIN to the output of the DAC.
MODES OF OPERATION
The AD5532 can be used in four different modes of operation.
These modes are set by two mode bits, the first two bits in the
serial word.
Table 9. Modes of Operation
Mode Bit 1
Mode Bit 2
Operating Mode
0
ISHA mode
0
1
DAC mode
1
0
Acquire and Read Back
1
Read Back
1. ISHA Mode
In this mode, a channel is addressed and that channel acquires
channel or all channels). MSB is written first.
2. DAC Mode
In this standard mode, a selected DAC register is loaded serially.
This requires a 24-bit write (10 bits to address the relevant DAC
plus an extra 14 bits of DAC data). MSB is written first. The
user must allow 400 ns (min) between successive writes in DAC
mode.
3. Acquire and Readback Mode
This mode allows the user to acquire VIN and read back the data
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and VIN is acquired in 16 μs (max).
Following the acquisition, after the next falling edge of SYNC,
the data in the relevant DAC register is clocked out onto the
DOUT line in a 14-bit serial format. The full acquisition time
must elapse before the DAC register data can be clocked out.
4. Readback Mode
Again, this is a Readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of SYNC, the data in the relevant DAC
register is clocked out onto the DOUT line in a 14-bit serial
format. The user must allow 400 ns (min) between the last
SCLK falling edge in the 10-bit write and the falling edge of
SYNC in the 14-bit read back. The serial write and read words
can be seen in
.
This feature allows the user to read back the DAC register code
of any of the channels. In DAC mode, this is useful in
verification of write cycles. In ISHA mode, readback is useful if
the system has been calibrated and the user wants to know what
code in the DAC corresponds to a desired voltage on VOUT. If
this voltage is required again, the user can input the code
directly to the DAC register without going through the
acquisition sequence.
00939-C-019
TRACK
VIN
DAC
ACQUISITION
CIRCUIT
VOUT1
BUSY
OUTPUT
STAGE
CONTROLLER
PIN
DRIVER
DEVICE
UNDER
TEST
THRESHOLD
VOLTAGE
ONLY ONE CHANNEL SHOWN FOR SIMPLICITY
AD5532
Figure 20. Typical ATE Circuit Using TRACK Input
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參數(shù)描述 |
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| AD5532ABCZ-3 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5532ABCZ-5 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5532B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AD5532B: 32-Channel. 14-Bit DAC with Precision Infinite Sample-and-Hold Mode (Rev A. 9/02) |
| AD5532BBC-1 | 制造商:Analog Devices 功能描述:DAC 32-CH 14-bit 74-Pin CSP-BGA Tray 制造商:Rochester Electronics LLC 功能描述:32 CHANNEL, 14-BIT DAC & SHA I.C. - Bulk 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Interface Ty |
| AD5532BBCZ-1 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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