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參數(shù)資料
| 型號： | AD5532ABCZ-2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32CH BIPO 74-CSPBGA |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 設置時間： | 30µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 34 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 623mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 74-LBGA，CSPBGA |
| 供應商設備封裝： | 74-CSPBGA（12x12） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | 45k |
| 配用： | EVAL-AD5532HSEBZ-ND - BOARD EVAL FOR AD5532HS EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532 |
AD5532
Rev. D | Page 17 of 20
PARALLEL INTERFACE (ISHA MODE ONLY)
The SER/PAR bit must be tied low to enable the parallel
interface and disable the serial interface. The parallel interface is
controlled by nine pins, as described in
.
Table 11.
Pin
Description
CS
Active low package select pin. This pin is shared
with the SYNC function for the serial interface.
WR
Active low write pin. The values on the address
pins are latched on a rising edge of WR.
A4–A0
Five address pins (A4 = MSB of address,
A0 = LSB). These are used to address the
relevant channel (out of a possible 32).
OFFSET_SEL
Offset select pin. This has the same function as
the Offset_Sel bit in the serial interface. When it
is high, the offset channel is addressed. The
address on A4–A0 is ignored in this case.
CAL
When this pin is high, all 32 channels acquire
VIN simultaneously. The acquisition time is then
45 μs (typ) and accuracy may be reduced.
MICROPROCESSOR INTERFACING
AD5532 to ADSP-21xx Interface
ADSP-21xx DSPs are easily interfaced to the AD5532 without
the need for extra logic.
A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence, data is
clocked out on each rising edge of the DSP serial clock and
clocked into the AD5532 on the falling edge of its SCLK. In
readback, 16 bits of data are clocked out of the AD5532 on each
rising edge of SCLK and clocked into the DSP on the rising
edge of SCLK. DIN is ignored. The valid 14 bits of data is
centered in the 16-bit RX register in this configuration. The
SPORT Control register should be set up as in Table 12.
Table 12.
TFSW = RFSW = 1
Alternate framing
INVRFS = INVTFS = 1
Active low frame signal
DTYPE = 00
Right justify data
ISCLK = 1
Internal serial clock
TFSR = RFSR = 1
Frame every word
IRFS = 0
External framing signal
ITFS = 1
Internal framing signal
SLEN = 1001
10-bit data-words (ISHA mode write)
SLEN = 0111
3 × 8-bit data-words (DAC mode write)
SLEN = 1111
16-bit data-words (Readback mode)
Figure 22 shows the connection diagram.
00939-C-021
DOUT
AD5532*
*ADDITIONAL PINS OMITTED FOR CLARITY
SYNC
DIN
SCLK
DR
TFS
DT
RFS
SCLK
ADSP-2101/
ADSP-2103*
Figure 22. AD5532 to ADSP-2101/ADSP-2103 Interface
AD5532 to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5532, the MOSI output drives the serial data line (DIN)
of the AD5532, and the MISO input is driven from DOUT. The
SYNC signal is derived from a port line (PC7). When data is
being transmitted to the AD5532, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. To transmit
10 data bits in ISHA mode, it is important to left-justify the data
in the SPDR register. PC7 must be pulled low to start a transfer.
It is taken high and pulled low again before other read/write
cycles can take place.
shows a connection diagram.
00939-C-022
AD5532*
*ADDITIONAL PINS OMITTED FOR CLARITY
MC68HC11*
DOUT
MISO
DIN
MOSI
SCLK
SCK
PC7
SYNC
Figure 23. AD5532 to MC68HC11 Interface
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD5532ABCZ-3 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5532ABCZ-5 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5532B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AD5532B: 32-Channel. 14-Bit DAC with Precision Infinite Sample-and-Hold Mode (Rev A. 9/02) |
| AD5532BBC-1 | 制造商:Analog Devices 功能描述:DAC 32-CH 14-bit 74-Pin CSP-BGA Tray 制造商:Rochester Electronics LLC 功能描述:32 CHANNEL, 14-BIT DAC & SHA I.C. - Bulk 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Interface Ty |
| AD5532BBCZ-1 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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