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參數(shù)資料
| 型號： | AD6653BCPZ-125 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 42/80頁 |
| 文件大?。?/td> | 1998K |
| 代理商： | AD6653BCPZ-125 |
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AD6653
SERIAL PORT INTERFACE (SPI)
The AD6653 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
The SPI gives the user added flexibility and customization,
depending on the application. Addresses are accessed using
the serial port and can be written to or read from via the port.
Memory is organized into bytes that can be further divided into
fields. These fields are documented in the Memory Map section.
For detailed operational information, see Application Note
AN-877,
Interfacing to High Speed ADCs via SPI,
at
www.analog.com
.
CONFIGURATION USING THE SPI
Three pins define the SPI of this ADC: the SCLK/DFS pin, the
SDIO/DCS pin, and the CSB pin (see Table 22). The SCLK/DFS
(serial clock) pin is used to synchronize the read and write data
presented from/to the ADC. The SDIO/DCS (serial data input/
output) pin is a dual-purpose pin that allows data to be sent and
read from the internal ADC memory map registers. The CSB
(chip select bar) pin is an active-low control that enables or
disables the read and write cycles.
Rev. 0 | Page 42 of 80
Table 22. Serial Port Interface Pins
Pin
Function
SCLK
Serial Clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
SDIO
Serial Data Input/Output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in
the timing frame.
CSB
Chip Select Bar. An active-low control that gates the
read and write cycles.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 79
and Table 5.
Other modes involving the CSB are available. The CSB can
be held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in a high impedance mode. This mode
turns on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase and its length is determined
by the W0 bit and the W1 bit.
All data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether a read command or a write
command is issued. This allows the serial data input/output (SDIO)
pin to change direction from an input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB-first mode or in LSB-first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this and
other features, see Application Note AN-877,
Interfacing to High
Speed ADCs via SPI,
at
www.analog.com
.
HARDWARE INTERFACE
The pins described in Table 22 comprise the physical interface
between the user programming device and the serial port of the
AD6653. The SCLK pin and the CSB pin function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in Application Note AN-812,
Microcontroller-
Based Serial Port Interface (SPI) Boot Circuit
.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD6653 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to AVDD or ground
during device power-on, they are associated with a specific
function. The Digital Outputs section describes the strappable
functions supported on the AD6653.
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PDF描述 |
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| AD6653BCPZ-150 | IF Diversity Receiver |
| AD6655BCPZ-1251 | IF Diversity Receiver |
| AD6655 | IF Diversity Receiver |
| AD6655-125EBZ1 | IF Diversity Receiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6653BCPZ-150 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 制造商:Analog Devices 功能描述:IC, RECEIVER, IF DIVERSITY, LFCSP64 |
| AD6654 | 制造商:Analog Devices 功能描述:- Bulk |
| AD6654/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 92.16 MSPS, 4-/6-Channel Wideband IF to Baseband Receiver |
| AD6654/PCBZ | 制造商:Analog Devices 功能描述:4/6CH WIDEBAND IF TO BASEBAND RCVR - Bulk |
| AD6654BBC | 功能描述:IC ADC 14BIT W/6CH RSP 256CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
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