參數(shù)資料
型號: AD6653BCPZ-125
廠商: ANALOG DEVICES INC
元件分類: 無繩電話/電話
英文描述: IF Diversity Receiver
中文描述: TELECOM, CELLULAR, BASEBAND CIRCUIT, QCC64
封裝: 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁數(shù): 7/80頁
文件大?。?/td> 1998K
代理商: AD6653BCPZ-125
AD6653
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = 1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, unless otherwise noted.
Rev. 0 | Page 7 of 80
Table 3.
AD6653BCPZ-125
Typ
AD6653BCPZ-150
Typ
Parameter
DIFFERENTIAL CLOCK INPUTS
(CLK+, CLK)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)
1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS)
2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO/DCS, SMI SDFS)
1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Temp
Min
Max
Min
Max
Unit
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS/LVPECL
1.2
AVDD 0.3
1.1 V
1.2
0
10
10
8
CMOS
AVDD 0.3
1.2
0
10
10
8
1.22
0
10
40
1.22
0
92
10
1.22
0
10
38
CMOS/LVDS/LVPECL
1.2
AVDD 0.3
1.1 V
1.2
0
10
10
8
V
V p-p
V
V
V
V
μA
μA
pF
V
V
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
0.2
6
AVDD + 1.6
AVDD
3.6
0.8
+10
+10
12
0.2
6
AVDD + 1.6
AVDD
3.6
0.8
+10
+10
12
4
10
4
10
CMOS
1.2
4
10
26
2
26
2
26
5
1.2
4
10
26
2
26
2
26
5
AVDD + 1.6
3.6
0.8
+10
+10
12
3.6
0.6
+10
132
3.6
0.6
135
+10
3.6
0.6
+10
128
AVDD 0.3
1.2
0
10
10
8
1.22
0
10
40
1.22
0
92
10
1.22
0
10
38
AVDD + 1.6
3.6
0.8
+10
+10
12
3.6
0.6
+10
132
3.6
0.6
135
+10
3.6
0.6
+10
128
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