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| 型號： | AD6653BCPZ-125 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 無繩電話/電話 |
| 英文描述： | IF Diversity Receiver |
| 中文描述： | TELECOM, CELLULAR, BASEBAND CIRCUIT, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 49/80頁 |
| 文件大?。?/td> | 1998K |
| 代理商： | AD6653BCPZ-125 |
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AD6653
MEMORY MAP REGISTER DESCRIPTION
For more information on functions controlled in Register 0x00
to Register 0xFF, see Application Note AN-877,
Interfacing to
High Speed ADCs via SPI
, at
www.analog.com
.
SYNC Control (Register 0x100)
Bit 7—Signal Monitor Sync Enable
Bit 7 enables the sync pulse from the external sync input to the
signal monitor block. The sync signal is passed when Bit 7 and
Bit 0 are high. This is continuous sync mode.
Bit 6—Half-Band Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the half-
band sync enable bit (Register 0x100, Bit 5) are high, Bit 6 allows
the NCO32 to synchronize following the first sync pulse it receives
and ignore the rest. If Bit 6 is set, Bit 5 of Register 0x100 resets
after this sync occurs.
Bit 5—Half-Band Sync Enable
Bit 5 gates the sync pulse to the half-band filter. When Bit 5
is set high, the sync signal causes the half-band to resynchro-
nize, starting at the half-band decimation phase selected in
Register 0x103, Bit 3. This sync is active only when the master
sync enable bit (Register 0x100, Bit 0) is high. This is continuous
sync mode.
Bit 4—NCO32 Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the
NCO32 sync enable bit (Register 0x100, Bit 3) are high, Bit 4
allows the NCO32 to sync following the first sync pulse it receives
and ignores the rest. Bit 3 of Register 0x100 resets after a sync
occurs if Bit 4 is set.
Bit 3—NCO32 Sync Enable
Bit 3 gates the sync pulse to the 32-bit NCO. When this bit is set
high, the sync signal causes the NCO to resynchronize, starting
at the NCO phase offset value. This sync is active only when the
master sync enable bit (Register 0x100, Bit 0) is high. This is
continuous sync mode.
Bit 2—Clock Divider Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the clock
divider sync enable bit (Register 0x100, Bit 1) are high, Bit 2
allows the clock divider to synchronize following the first sync
pulse it receives and ignore the rest. Bit 1 of Register 0x100
resets after it synchronizes.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal
is passed when Bit 1 and Bit 0 are high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
Rev. 0 | Page 49 of 80
f
S
/8 Output Mix Control (Register 0x101)
Bits[7:6]—Reserved
Bits[5:4]—f
S
/8 Start State
Bit 5 and Bit 4 set the starting phase of the f
S
/8 output mix.
Bits[3:2]—Reserved
Bit 1—f
S
/8 Next Sync Only
If the master sync enable bit (Register 0x100, Bit 0) and the f
S
/8
sync enable bit (Register 0x101, Bit 0) are high, Bit 1 allows the
f
S
/8 output mix to synchronize following the first sync pulse it
receives and ignore the rest. Bit 0 of Register 0x100 resets after it
synchronizes.
Bit 0—f
S
/8 Sync Enable
Bit 0 gates the sync pulse to the f
S
/8 output mix. This sync is
active only when the master sync enable bit (Register 0x100,
Bit 0) is high. This is continuous sync mode.
FIR Filter and Output Mode Control (Register 0x102)
Bits[7:4]—Reserved
Bit 3—FIR Gain
When Bit 3 is set high, the FIR filter path, if enabled, has a gain
of 1. When Bit 3 set low, the FIR filter path has a gain of 2.
Bit 2—f
S
/8 Output Mix Disable
Bit 2 disables the f
S
/8 output mix when enabled. Bit 2 should be
set along with Bit 1 to enable complex output mode.
Bit 1—Complex Output Mode Enable
Setting Bit 1 high enables complex output mode.
Bit 0—FIR Filter Enable
When set high, Bit 0 enables the FIR filter. When Bit 0 is
cleared, the FIR filter is bypassed and shut down for power
savings.
Digital Filter Control (Register 0x103)
Bits[7:4]—Reserved
Bit 3—Half-Band Decimation Phase
When set high, Bit 3 uses the alternate phase of the decimating
half-band filter.
Bit 2—Spectral Reversal
Bit 2 enables the spectral reversal feature of the half-band filter.
Bit 1—High-Pass/Low-Pass Select
Bit 1 enables the high-pass mode of the half-band filter when
set high. Setting this bit low enables the low-pass mode (default).
Bit 0—Reserved
Bit 0 reads back as a 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6653BCPZ-150 | 制造商:Analog Devices 功能描述:IF DIVERSITY RCVR 64LFCSP EP - Trays 制造商:Analog Devices 功能描述:IC RECEIVER IF DIVERSITY LFCSP64 制造商:Analog Devices 功能描述:IC, RECEIVER, IF DIVERSITY, LFCSP64 |
| AD6654 | 制造商:Analog Devices 功能描述:- Bulk |
| AD6654/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 92.16 MSPS, 4-/6-Channel Wideband IF to Baseband Receiver |
| AD6654/PCBZ | 制造商:Analog Devices 功能描述:4/6CH WIDEBAND IF TO BASEBAND RCVR - Bulk |
| AD6654BBC | 功能描述:IC ADC 14BIT W/6CH RSP 256CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
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