參數(shù)資料
型號(hào)： AD6653BCPZ-150
廠商： ANALOG DEVICES INC
元件分類(lèi)： 無(wú)繩電話/電話
英文描述： IF Diversity Receiver
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁(yè)數(shù)： 26/80頁(yè)
文件大?。?/td> 1998K
代理商： AD6653BCPZ-150
AD6653
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input common-
mode swing. If the source impedances on each input are matched,
there should be little effect on SNR performance. Figure 51 shows
a typical single-ended input configuration.
Rev. 0 | Page 26 of 80
2V p-p
R
R
C
49.9
0.1μF
10μF
10μF
0.1μF
AVDD
1k
1k
1k
1k
AD6653
AVDD
VIN+
VIN–
0
Figure 51. Single-Ended Input Configuration
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD6653.
The input range can be adjusted by varying the reference voltage
applied to the AD6653, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in the sections that follow. The Reference
Decoupling section describes the best practices PCB layout of
the reference.
Internal Reference Connection
A comparator within the AD6653 detects the potential at the
SENSE pin and configures the reference into four possible modes,
which are summarized in Table 11. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 52), setting VREF to 1.0 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a 0.5 V
reference output.
VREF
SENSE
0.5V
AD6653
SELECT
LOGIC
0.1μF
1.0μF
VIN–A/VIN–B
VIN+A/VIN+B
ADC
CORE
0
Figure 52. Internal Reference Configuration
If a resistor divider is connected externally to the chip, as shown
in Figure 53, the switch again sets to the SENSE pin. This puts
the reference amplifier in a noninverting mode with the VREF
output defined as follows:
1
×
=
R1
R2
.
VREF
5
0
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
0.5V
AD6653
SELECT
LOGIC
VIN–A/VIN–B
VIN+A/VIN+B
ADC
CORE
VREF
SENSE
0.1μF
1.0μF
R2
R1
0
Figure 53. Programmable Reference Configuration
Table 11. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
SENSE Voltage
AVDD
VREF
Resulting VREF (V)
N/A
0.5
+
×
1
5
Resulting Differential Span (V p-p)
2 × external reference
1.0
Programmable Reference
0.2 V to VREF
R1
R2
(see Figure 53)
2 × VREF
Internal Fixed Reference
AGND to 0.2 V
1.0
2.0
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AD6654 制造商:Analog Devices 功能描述:- Bulk
AD6654/PCB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:14-Bit, 92.16 MSPS, 4-/6-Channel Wideband IF to Baseband Receiver
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AD6654BBC 功能描述:IC ADC 14BIT W/6CH RSP 256CSPBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類(lèi)型:2 個(gè)單端，單極
AD6654BBCZ 功能描述:IC ADC 14BIT W/6CH RSP 256CSPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類(lèi)型:2 個(gè)單端，單極
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