參數(shù)資料
型號： AD6653BCPZ-150
廠商： ANALOG DEVICES INC
元件分類： 無繩電話/電話
英文描述： IF Diversity Receiver
中文描述： TELECOM, CELLULAR, BASEBAND CIRCUIT, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁數(shù)： 28/80頁
文件大?。?/td> 1998K
代理商： AD6653BCPZ-150
AD6653
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 59. The
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516
clock drivers offer excellent
jitter performance.
Rev. 0 | Page 28 of 80
100
0.1μF
0.1μF
0.1μF
0.1μF
240
240
AD951x
PECL DRIVER
50k
50k
CLK–
CLK+
ADC
AD6653
INPUT
CLOCK
INPUT
0
Figure 59. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 60. The
AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516
clock
drivers offer excellent jitter performance.
100
0.1μF
0.1μF
0.1μF
0.1μF
50k
50k
CLK–
CLK+
ADC
AD6653
INPUT
CLOCK
INPUT
LVDS DRIVER
0
Figure 60. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
the CLK+ pin should be driven directly from a CMOS gate, and the
CLK pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 61). CLK+ can be
driven directly from a CMOS gate. Although the CLK+ input
circuit supply is AVDD (1.8 V), this input is designed to withstand
input voltages of up to 3.6 V making the selection of the drive logic
voltage very flexible.
OPTIONAL
100
0.1μF
0.1μF
0.1μF
39k
50
CLK–
CLK+
ADC
AD6653
V
CC
1k
1k
CLOCK
INPUT
CMOS DRIVER
0
Figure 61. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)
OP100
0.1μF
0.1μF
0.1μF
V
CC
50
CLK–
CLK+
ADC
AD6653
1k
1k
CLOCK
INPUT
AD951x
CMOS DRIVER
0
Figure 62. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
Input Clock Divider
The AD6653 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
The AD6653 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state.
This synchronization feature allows multiple parts to have their
clock dividers aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics.
The AD6653 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows the user to
provide a wide range of clock input duty cycles without affecting
performance of the AD6653. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 44.
Jitter on the rising edge of the input clock is still of paramount
concern and is not easily reduced by the internal stabilization
circuit. The duty cycle control loop does not function for clock
rates less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered when the clock rate
can change dynamically. A wait time of 1.5 μs to 5 μs is required
after a dynamic clock frequency increase or decrease before the
DCS loop is relocked to the input signal. During the time period
that the loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (f
IN
) due to jitter (t
J
) can be calculated by
[
J
IN
t
πf
SNR
×
=
2
log
20
]
In the equation, the rms aperture jitter represents the root mean
square of all jitter sources, which include the clock input, the
analog input signal, and the ADC aperture jitter specification.
IF undersampling applications are particularly sensitive to jitter,
as shown in Figure 63.
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相關代理商/技術參數(shù)
參數(shù)描述
AD6654 制造商:Analog Devices 功能描述:- Bulk
AD6654/PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 92.16 MSPS, 4-/6-Channel Wideband IF to Baseband Receiver
AD6654/PCBZ 制造商:Analog Devices 功能描述:4/6CH WIDEBAND IF TO BASEBAND RCVR - Bulk
AD6654BBC 功能描述:IC ADC 14BIT W/6CH RSP 256CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極
AD6654BBCZ 功能描述:IC ADC 14BIT W/6CH RSP 256CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極
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