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| 型號： | AD7834BR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT QUAD SRL 28-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 465mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 100k |
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AD7834/AD7835
Rev. D | Page 21 of 28
CLR
LDAC
FSYNC
SCLK
DIN
XF
FSX
CLKX
DX
AD78341
TMS32020/
TMS320C251
CLOCK/
TIMER
1ADDITIONAL PINS OMITTED FOR CLARITY
01006-030
First, data can be transferred using the autobuffering feature of
the ADSP-2101, sending two 12-bit words directly after each
other. This ensures a continuous transmit frame synchron-
ization (TFS ) pulse. Second, the first data word is loaded to the
serial port, the subsequent generated interrupt is trapped, and
then the second data word is sent immediately after the first.
Again, this produces a continuous TFS pulse that frames the
24 data bits.
AD7834 TO DSP56000/DSP56001 INTERFACE
Figure 29 shows a serial interface between the AD7834 and the
DSP56000/DSP56001. The serial port is configured for a word
length of 24 bits, gated clock, and FSL0 and FSL1 control bits
each set to 0. Normal mode synchronous operation is selected,
which allows the use of SC0 and SC1 as outputs controlling
Figure 30. AD7834 to TMS32020/TMS320C25 Interface
INTERFACING THE AD7835—16-BIT INTERFACE
The AD7835 can be interfaced to a variety of microcontrollers
or DSP processors, both 8-bit and 16-bit. Figure 31 shows the
AD7835 interfaced to a generic 16-bit microcontroller/DSP
processor.
CLR
LDAC
and
, respectively. The framing signal on SC2 has to
be inverted before being applied to
BYSHF is tied to VCC in this interface. The lower
address lines from the processor are connected to A0, A1, and
A2 on the AD7835 as shown. The upper address lines are
decoded to provide a chip select signal for the AD7835. They
are also decoded, in conjunction with the lower address lines if
need be, to provide an
FSYNC. SCK is internally
generated on the DSP56000/DSP56001 and is applied to SCLK
on the AD7834. Data from the DSP56000/DSP56001 is valid on
the falling edge of SCK.
CLR
LDAC
FSYNC
SCLK
DIN
SC0
SC1
SC2
SCK
STD
AD78341
DSP56000/
DSP560011
1ADDITIONAL PINS OMITTED FOR CLARITY
01006-029
Figure 29. AD7834 to DSP56000/DSP56001 Interface
AD7834 TO TMS32020/TMS320C25 INTERFACE
A serial interface between the AD7834 and the TMS32020/
TMS320C25 DSP processor is shown in Figure 30. The
CLKX and FSX signals for the TMS32020/TMS32025 are
generated using an external clock/timer circuit. The CLKX and
FSX pins are configured as inputs. The TMS32020/ TMS320C25
are set up for an 8-bit serial data length. Data can then be written
to the AD7834 by writing three bytes to the serial port of the
TMS32020/TMS320C25. In the configuration shown in Figure
30, the CLR input on the AD7834 is controlled by the XF output
on the TMS32020/TMS320C25. The clock/timer circuit controls
the LDAC input on the AD7834. Alternatively, LDAC can also be
tied to ground to allow automatic update of the DAC latches after
each transfer.
LDAC
signal. Alternatively,
can be
driven by an external timing circuit or just tied low. The data
lines of the processor are connected to the data lines of the
AD7835. Selection options available for the DACs are provided
in Table 11.
VCC
ADDRESS
DECODE
AD78351
D13
D0
CS
LDAC
A2
A1
A0
WR
BYSHF
D13
D0
A2
A1
A0
R/W
DATABUS
UPPER BITS OF
ADDRESS BUS
MICROCONTROLLER/
DSP
PROCESSOR1
1ADDITIONAL PINS OMITTED FOR CLARITY
01
00
6-
0
31
Figure 31. AD7835 16-Bit Interface
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