參數資料
型號： AD7834BR-REEL
廠商： Analog Devices Inc
文件頁數： 6/28頁
文件大?。?/td> 0K
描述： IC DAC 14BIT QUAD SRL 28-SOIC
產品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 1,000
設置時間： 10µs
位數： 14
數據接口： 串行
轉換器數目： 4
電壓電源： 模擬和數字，雙 ±
功率耗散（最大）： 465mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應商設備封裝： 28-SOIC W
包裝： 帶卷 (TR)
輸出數目和類型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 100k
AD7834/AD7835
Rev. D | Page 14 of 28
THEORY OF OPERATION
DAC ARCHITECTURE
Each channel consists of a segmented 14-bit R-2R voltage-mode
DAC. The full-scale output voltage range is equal to the entire
reference span of VREF(+) – VREF(). The DAC coding is straight
binary; all 0s produce an output of VREF(); all 1s produce an
output of VREF(+) 1 LSB.
The analog output voltage of each DAC channel reflects the
contents of its own DAC latch. Data is transferred from the
external bus to the input register of each DAC latch on a per
channel basis. The AD7835 has a feature whereby the A2 pin
data can be transferred from the input databus to all four input
registers simultaneously.
Bringing the CLR line low switches all the signal outputs, VOUT1
to VOUT4, to the voltage level on the DSG pin. The signal
outputs are held at this level after the removal of the CLR signal
and do not switch back to the DAC outputs until the LDAC
signal is exercised.
DATA LOADING—AD7834 SERIAL INPUT DEVICE
A write operation transfers 24 bits of data to the AD7834. The
first 8 bits are control data and the remaining 16 bits are DAC
data (see Figure 18). The control data identifies the DAC chan-
nel to be updated with new data and which of 32 possible
packages the DAC resides in. In any communication with the
device, the first 8 bits must always be control data.
The DAC output voltages, VOUT1 to VOUT4, can be updated to
reflect new data in the DAC input registers in one of two ways.
The first method normally keeps LDAC high and only pulses
LDAC low momentarily to update all DAC latches simultan-
eously with the contents of their respective input registers. The
second method ties LDAC low and channel updating occurs on
a per channel basis after new data has been clocked into the
AD7834. With LDAC low, the rising edge of FSYNC transfers
the new data directly into the DAC latch, updating the analog
output voltage.
Data being shifted into the AD7834 enters a 24-bit long shift
register. If more than 24 bits are clocked in before FSYNC goes
high, the last 24 bits transmitted are used as the control data
and DAC data.
Individual bit functions are shown in Figure 18.
D23
D23 determines whether the following 23 bits of address and
data should be used or ignored. This is effectively a software
chip select bit. D23 is the first bit to be transmitted in the 24-bit
long word.
Table 9. D23 Control
D23
Control Function
0
Ignore the following 23 bits of information.
1
Use the following 23 bits of address and data as normal.
D22 and D21
D22 and D21 are decoded to select one of the four DAC chan-
nels within a device, as shown in Table 10.
Table 10. D22, D21 Control
D22
D21
Control Function
0
Select Channel 1
0
1
Select Channel 2
1
0
Select Channel 3
1
Select Channel 4
D20 to D16
D20 and D16 determine the package address. The five address
bits allow up to 32 separate packages to be individually decoded.
Successful decoding is accomplished when these five bits match
up with the five hardwired pins on the physical package.
D15 to D0
D15 and D0 provide DAC data to be loaded into the identified
DAC input register. This data must have two leading 0s followed
by 14 bits of data, MSB first. The MSB is in location D13 of the
24-bit data stream.
DATA LOADING—AD7835 PARALLEL LOADING
DEVICE
Data is loaded into the AD7835 in either straight 14-bit wide
words or in two 8-bit bytes.
In systems that transfer 14-bit wide data, the BYSHF input
should be hardwired to VCC. This sets up the AD7835 as a
straight 14-bit parallel-loading DAC.
In 8-bit bus systems where it is required to transfer data in two
bytes, it is necessary to have the BYSHF input under logic control.
In such a system, the top six pins of the device databus, DB8 to
DB13, must be hardwired to DGND. New low byte data is
loaded into the lower eight places of the selected input register
by carrying out a write operation while holding BYSHF high.
A second write operation is subsequently executed with BYSHF
low and the 6 MSBs on the DB0 to DB5 inputs (DB5 = MSB).
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