參數(shù)資料
型號(hào)： AD7834BR-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/28頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT QUAD SRL 28-SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
設(shè)置時(shí)間： 10µs
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
功率耗散（最大）： 465mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 100k
AD7834/AD7835
Rev. D | Page 13 of 28
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error. It is normally
expressed in LSBs or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
DC Crosstalk
Although the common input reference (IR) voltage signals are
internally buffered, small IR drops in individual DAC reference
inputs across the die mean that an update to one channel
produces a dc output change in one or more channel outputs.
The four DAC outputs are buffered by op amps sharing
common VDD and VSS power supplies. If the dc load current
changes in one channel due to an update, a further dc change
occurs in one or more of the channel outputs. This effect is
most obvious at high load currents and is reduced as the load
currents are reduced. With high impedance loads, the effect is
virtually unmeasurable.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-secs. It is measured with the reference inputs
connected to 0 V and the digital inputs toggled between all
1s and all 0s.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from the reference input of one DAC that appears at the
output of the other DAC. It is expressed in decibels (dB). The
AD7834 has no specification for channel-to-channel isolation
because it has one reference for all DACs. Channel-to-channel
isolation is specified for the AD7835.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is defined as the glitch impulse that
appears at the output of one converter due to both the digital
change and the subsequent analog output (O/P) change at
another converter. It is specified in nV-secs.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the digital crosstalk and is specified in nV-secs.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on its digital inputs can be capacitively coupled both across and
through the device to show up as noise on the VOUT pins. This
noise is digital feedthrough.
DC Output Impedance
DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.
Full-Scale Error
Full-scale error is the error in DAC output voltage when all 1s
are loaded into the DAC latch. Ideally, the output voltage, with
all 1s loaded into the DAC latch, should be VREF(+) – 1 LSB.
Full-scale error does not include zero-scale error.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when
all 0s are loaded into the DAC latch. Ideally, the output voltage,
with all 0s in the DAC latch, is equal to VREF(). Zero-scale
error is due mainly to offsets in the output amplifier.
Gain Error
Gain error is defined as (full-scale error) (zero-scale error).
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