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參數(shù)資料
| 型號： | AD7834BR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT QUAD SRL 28-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 465mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 100k |
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AD7834/AD7835
Rev. D | Page 17 of 28
CONTROLLED POWER-ON OF THE OUTPUT STAGE
DAC
G1
G3
VOUT
R
G6
G4
G5
G2
DSG
01006-023
A block diagram of the output stage of the AD7834/AD7835 is
shown in Figure 21. It is capable of driving a load of 10 kΩ in
parallel with 200 pF. G1 to G6 are transmission gates used to
control the power-on voltage present at VOUT. G1 and G2 are also
used in conjunction with the CLR input to set VOUT to the user-
defined voltage present at the DSG pin.
DAC
G1
G3
VOUT
R
G6
G4
G5
G2
DSG
01006-021
Figure 23. Output Stage with VDD > 10 V and CLR Low
VOUT is disconnected from the DSG pin by the opening of G5
but tracks the voltage present at DSG via the unity gain buffer.
Figure 21. Block Diagram of AD7834/AD7835 Output Stage
POWER-ON WITH CLR LOW, LDAC HIGH
The output stage of the AD7834/AD7835 is designed to allow
output stability during power-on. If CLR is kept low during
power-on, and power is applied to the part, G1, G4, and G6 are
DAC
G1
G3
VOUT
R
G6
G4
G5
G2
DSG
01006-022
Figure 22. Output Stage with VDD < 10 V
VOUT is kept within a few hundred millivolts of DSG via G5
and R. R is a thin-film resistor between DSG and VOUT. The
output amplifier is connected as a unity gain buffer via G3, and
the DSG voltage is applied to the buffer input via G2. The
amplifier output is thus at the same voltage as the DSG pin. The
output stage remains configured as in Figure 22 until the
voltage at VDD and VSS reaches approximately ±10 V. At this
point, the output amplifier has enough headroom to handle
signals at its input and has also had time to settle. The internal
power-on circuitry opens G3 and G5 and closes G4 and G6 (see
Figure 23). As a result, the output amplifier is connected in
unity gain mode via G4 and G6. The DSG voltage is still applied
to the noninverting input via G2. This voltage appears at VOUT.
POWER-ON WITH LDAC LOW, CLR HIGH
LDAC
In many applications of the AD7834/AD7835,
is kept
continuously low, updating the DAC after each valid data
transfer. If LDAC is low when power is applied, G1 is closed and
G2 is open, connecting the output of the DAC to the input of the
output amplifier. G3 and G5 are closed and G4 and G6 are open,
connecting the amplifier as a unity gain buffer, as before. VOUT is
connected to DSG via G5 and R (a thin-film resistance between
DSG and VOUT) until VDD and VSS reach approximately ±10 V.
Then, the internal power-on circuitry opens G3 and G5 and
this point, VOUT is at the same voltage as the DAC output.
DAC
G1
G3
VOUT
R
G6
G4
G5
G2
DSG
01006-024
LDAC
Figure 24. Output Stage with
Low
LOADING THE DAC AND USING THE CLR INPUT
LDAC
When
The voltage at VOUT now follows the voltage present at the out-
put of the DAC. The output stage remains connected in this
manner until a CLR signal is applied. Then, the situation reverts
DSG until LDAC goes low. This reconnects the DAC output to
the unity gain buffer.
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| AD7834BRZ | 功能描述:IC DAC 14BIT QUAD SRL 28-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD7834BRZ-REEL | 功能描述:IC DAC 14BIT QUAD SERIAL 28SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD7834SQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Quad 14-Bit DAC |
| AD7835 | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Quad 14-Bit DAC |
| AD7835AP | 功能描述:IC DAC 14BIT QUAD PARA 44-PLCC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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