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參數(shù)資料
| 型號(hào)： | AD7834BR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 16/28頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT QUAD SRL 28-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 10µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 465mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 100k |
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AD7834/AD7835
Rev. D | Page 23 of 28
APPLICATIONS INFORMATION
Figure 34 shows a 5-channel isolated interface to the AD7834.
Multiple devices are connected to the outputs of the opto-coupler
and controlled as for serial interfacing. To reduce the number of
opto-isolators, the
SERIAL INTERFACE TO MULTIPLE AD7834S
Figure 33 shows how the package address pins of the AD7834
are used to address multiple AD7834s. This figure shows only
10 devices, but up to 32 AD7834s can each be assigned a unique
address by hardwiring each of the package address pins to VCC
or DGND. Normal operation of the device occurs when
PAEN line doesn’t need to be controlled if it
is not used. If the PAEN line is not controlled by the microcon-
troller, it should be tied low at each device. If simultaneous updat-
ing of the DACs is not required, the
PAEN
is low. When serial data is being written to the AD7834s, only
the device with the same package address as the package address
contained in the serial data accepts data into the input registers.
Conversely, if
LDAC pin on each part can
be tied permanently low and another opto-isolator is not needed.
MICROCONTROLLER
CONTROL OUT
SYNC OUT
SERIAL CLOCK OUT
SERIAL DATA OUT
OPTO-COUPLER
VCC
TO PAENs
TO LDACs
TO FSYNCs
TO SCLKs
TO DINs
01
00
6-
03
4
PAEN is high, the package address is ignored, and
the data is loaded into the same channel on each package.
The primary limitation with multiple packages is the output
update rate. For example, if an output update rate of 10 kHz is
required, 100 μs are available to load all DACs. Assuming a
serial clock frequency of 10 MHz, it takes 2.5 μs to load data to
one DAC. Thus, 40 DACs or 10 packages can be updated in this
time. As the update rate requirement decreases, the number of
possible packages increases.
1ADDITIONAL PINS OMITTED FOR CLARITY
AD78341
DEVICE 0
PAEN
LDAC
FSYNC
SCLK
DIN
PA0
PA1
PA2
PA3
PA4
VCC
MICROCONTROLLER
CONTROL OUT
SYNC OUT
SERIAL CLOCK OUT
SERIAL DATA OUT
AD78341
DEVICE 1
PAEN
LDAC
FSYNC
SCLK
DIN
PA0
PA1
PA2
PA3
PA4
AD78341
DEVICE 9
PAEN
LDAC
FSYNC
SCLK
DIN
PA0
PA1
PA2
PA3
PA4
01
00
6-
03
3
Figure 34. Opto-Isolated Interface
AUTOMATED TEST EQUIPMENT
The AD7834/AD7835 are particularly suited for use in an
automated test environment. Figure 35 shows the AD7835
providing the necessary voltages for the pin driver and the
window comparator in a typical ATE pin electronics configur-
ation. Two AD588s are used to provide reference voltages for
the AD7835. In the configuration shown, the AD588s are
configured so that the voltage at Pin 1 is 5 V greater than the
voltage at Pin 9 and the voltage at Pin 15 is 5 V less than the
voltage at Pin 9.
One
is used as a reference for DAC 1 and DAC 2. These
DACs are used to provide high and low levels for the pin driver.
The pin driver can have an associated offset. This can be nulled
by applying an offset voltage to Pin 9 of the AD588. First, the
code 1000 . . . 0000 is loaded into the DAC 1 latch, and the pin
driver output is set to the DAC 1 output. The VOFFSET voltage is
adjusted until 0 V appears between the pin driver output and
DUT GND. This causes both VREF(+)A and VREF()A to be off-
set with respect to AGND by an amount equal to VOFFSET.
However, the output of the pin driver varies from 5 V to +5 V
with respect to DUT GND as the DAC input code varies from
000 . . . 000 to 111 . . . 111. The VOFFSET voltage is also applied to
the DSGA pin. When a clear is performed on the AD7835, the
output of the pin driver is 0 V with respect to DUT GND.
Figure 33. Serial Interface to Multiple AD7834s
OPTO-ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD7834
makes it ideal for opto-isolated interfaces because the number
of interface lines is kept to a minimum.
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