LC2MOS
Quad 14-Bit DACs
AD7834/AD7835
Rev. D
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FEATURES
Four 14-bit DACs in one package
AD7834—serial loading
AD7835—parallel 8-bit/14-bit loading
Voltage outputs
Power-on reset function
Maximum/minimum output voltage range of ±8.192 V
Maximum output voltage span of 14 V
Common voltage reference inputs
User-assigned device addressing
Clear function to user-defined voltage
Surface-mount packages
AD7834—28-lead SOIC and PDIP
AD7835—44-lead MQFP and PLCC
APPLICATIONS
Process control
Automatic test equipment
General-purpose instrumentation
GENERAL DESCRIPTION
The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output
voltages in the range ±8.192 V with a maximum span of 14 V.
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading 0s,
into one via DIN, SCLK, and FSYNC. The AD7834 has five
dedicated package address pins, PA0 to PA4, that can be wired
to AGND or VCC to permit up to 32 AD7834s to be individually
addressed in a multipackage application.
The AD7835 can accept either 14-bit parallel loading or double-
byte loading, where right-justified data is loaded in one 8-bit
byte and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the WR, CS,
BYSHF, and DAC channel address pins, A0 to A2.
With each device, the LDAC signal is used to update all four
DAC outputs simultaneously, or individually, on reception of
new data. In addition, for each device, the asynchronous CLR
input can be used to set all signal outputs, VOUT1 to VOUT4, to
the user-defined voltage level on the device sense ground pin,
DSG. On power-on, before the power supplies have stabilized,
internal circuitry holds the DAC output voltage levels to within
±2 V of the DSG potential. As the supplies stabilize, the DAC
output levels move to the exact DSG potential (assuming CLR is
exercised).
The AD7834 is available in a 28-lead 0.3" SOIC package and a
28-lead 0.6" PDIP package, and the AD7835 is available in a
44-lead MQFP package and a 44-lead PLCC package.
FUNCTIONAL BLOCK DIAGRAMS
×1
DAC 1
LATCH
INPUT
REGISTER
1
VCC
VDD
VSS
VREF(–) VREF(+)
VOUT 1
PAEN
PA0
PA1
PA2
PA3
PA4
CONTROL
LOGIC
AND
ADDRESS
DECODE
SERIAL-TO-
PARALLEL
CONVERTER
DIN
SCLK
×1
DAC 2
LATCH
INPUT
REGISTER
2
×1
DAC 3
LATCH
×1
DAC 4
LATCH
INPUT
REGISTER
4
AD7834
VOUT 2
VOUT 3
VOUT 4
AGND
DGND
DSG
FSYNC
LDAC
CLR
INPUT
REGISTER
3
DAC 1
DAC 2
DAC 3
DAC 4
01
00
6-
00
1
×1
DAC 1
LATCH
INPUT
REGISTER
1
VCC
VDD
VSS
VREF(–)A VREF(+)A
VOUT1
BYSHF
DB13
DB0
A0
A1
A2
CS
×1
DAC 2
LATCH
DAC 2
INPUT
REGISTER
2
×1
DAC 3
LATCH
INPUT
REGISTER
3
×1
DAC 4
LATCH
INPUT
REGISTER
4
DAC 1
AD7835
VOUT2
VOUT3
VOUT4
AGND
DGND
LDAC
DSGB
CLR
DSGA
DAC 4
DAC 3
VREF(–)B VREF(+)B
ADDRESS
DECODE
INPUT
BUFFER
WR
14
01
00
6-
0
02
Figure 1. AD7834
Figure 2. AD7835