參數(shù)資料
型號: AD7835ASZ
廠商: Analog Devices Inc
文件頁數(shù): 28/28頁
文件大小: 0K
描述: IC DAC 14BIT QUAD PARA 44-MQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1
設(shè)置時間: 10µs
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 465mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-QFP
供應(yīng)商設(shè)備封裝: 44-MQFP(10x10)
包裝: 托盤
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 100k
產(chǎn)品目錄頁面: 785 (CN2011-ZH PDF)
AD7834/AD7835
Rev. D | Page 9 of 28
9
10
11
12
13
7
8
16
17
14
15
244
3
4
5
642 41 40
43
35
36
37
38
39
33
34
31
32
29
30
18 19 20 21 22 23 24 25 26 27 28
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
DB4
DB5
DB6
DB1
CS
WR
V
CC
DGND
DB0
DB2
DB3
NC
DSGB
VOUT3
VOUT4
DB13
DB12
DB11
AD7835
NC
DSGA
VOUT1
VOUT2
NC
A2
A1
NC = NO CONNECT
A0
CLR
LDAC
BYSHF
DB10
DB9
DB8
DB7
NC
V
RE
F
(+)A
NC
V
SS
V
DD
AGND
NC
V
RE
F
(+)B
V
RE
F
(–
)A
NC
V
RE
F
(–
)B
01006-008
1
12 13 14 15 16 17 18 19 20 21 22
3
4
5
6
7
1
2
10
11
8
9
40 39 38
41
42
43
44
36 35 34
37
29
30
31
32
27
28
25
26
23
24
33
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
NC
DSGB
VOUT3
VOUT4
DB13
DB12
DB11
AD7835
DB1
CS
WR
V
CC
DGND
DB0
DB2
DB3
DB4
DB5
DB6
NC
DSGA
VOUT1
VOUT2
NC
A2
A1
NC = NO CONNECT
A0
CLR
LDAC
BYSHF
DB10
DB9
DB8
DB7
NC
V
RE
F
(–
)A
V
RE
F
(+)A
NC
V
SS
V
DD
AGND
NC
V
RE
F
(+)B
V
RE
F
(–)B
01006-007
Figure 7. AD7835 MQFP Pin Configuration
Figure 8. AD7835 PLCC Pin Configuration
Table 8. AD7835 Pin Function Descriptions
Pin No.
MQFP
Pin No. PLCC
Pin Mnemonic
Description
NC
No Connect.
1, 5, 33, 34,
37, 41, 44
3, 6, 7, 11, 39,
40, 43
2
8
DSGA
Device Sense Ground A Input. Used in conjunction with the CLR input for power-on
protection of the DACs. When CLR is low, DAC outputs VOUT1 and VOUT2 are forced to the
potential on the DSGA pin.
VOUT1 to VOUT4
3, 4, 31, 30
9, 10, 37, 36
DAC Outputs.
8, 7, 6
14, 13, 12
A0, A1, A2
Address Inputs. A0 and A1 are decoded to select one of the four input latches for a data
transfer. A2 is used to select all four DACs simultaneously.
9
15
CLR
Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low,
all analog outputs are switched to the externally set potentials on the DSG pins (VOUT1
and VOUT2 follow DSGA, and VOUT3 and VOUT4 follow DSGB). When CLR is brought high, the
signal outputs remain at the DSG potentials until LDAC is brought low. When LDAC is
brought low, the analog outputs are switched back to reflect their individual DAC output
levels. As long as CLR remains low, the LDAC signals are ignored, and the signal outputs
remain switched to the potential on the DSG pins.
10
16
LDAC
Load DAC Input (Level Sensitive). This input signal, in conjunction with the WR and CS
input signals, determines how the analog outputs are updated. If LDAC is maintained
high while new data is being loaded into the device’s input registers, no change occurs
on the analog outputs. Subsequently, when LDAC is brought low, the contents of all four
input registers are transferred into their respective DAC latches, updating the analog
outputs simultaneously. Alternatively, if LDAC is brought low while new data is being
entered, the addressed DAC latch and corresponding analog output are updated
immediately on the rising edge of WR.
11
17
BYSHF
Byte Shift Input. When low, it shifts the data on DB0 to DB7 into the DB8 to DB13 half of
the input register.
12
18
CS
Level-Triggered Chip Select Input (Active Low). The device is selected when this input is
low.
13
19
WR
Level-Triggered Write Input (Active Low). When active, it is used in conjunction with CS
to write data over the input databus.
14
20
VCC
Logic Power Supply: 5 V ± 5%.
15
21
DGND
Digital Ground.
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