VCC = 5 V ± 5%; V
參數(shù)資料
型號: AD7835ASZ
廠商: Analog Devices Inc
文件頁數(shù): 25/28頁
文件大小: 0K
描述: IC DAC 14BIT QUAD PARA 44-MQFP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時間: 10µs
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 465mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 44-QFP
供應(yīng)商設(shè)備封裝: 44-MQFP(10x10)
包裝: 托盤
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): 100k
產(chǎn)品目錄頁面: 785 (CN2011-ZH PDF)
AD7834/AD7835
Rev. D | Page 6 of 28
TIMING SPECIFICATIONS
VCC = 5 V ± 5%; VDD = 11.4 V to 15.75 V; VSS = 11.4 V to 15.75 V; AGND = DGND = 0 V1.
Table 4.
Parameter
Limit at TMIN, TMAX
Unit
Description
AD7834-SPECIFIC
100
ns min
SCLK cycle time
50
ns min
SCLK low
30
ns min
SCLK high time
t4
30
ns min
FSYNC, PAEN setup time
t5
40
ns min
FSYNC, PAEN hold time
t6
30
ns min
Data setup time
t7
10
ns min
Data hold time
t8
0
ns min
LDAC to FSYNC setup time
t9
40
ns min
LDAC to FSYNC hold time
t21
20
ns min
Delay between write operations
AD7835-SPECIFIC
t11
15
ns min
A0, A1, A2, BYSHF to CS setup time
t12
15
ns min
A0, A1, A2, BYSHF to CS hold time
t13
0
ns min
CS to WR setup time
t14
0
ns min
CS to WR hold time
t15
40
ns min
WR pulse width
t16
40
ns min
Data setup time
t17
10
ns min
Data hold time
t18
0
ns min
LDAC to CS setup time
t19
0
ns min
CS to LDAC setup time
t20
0
ns min
LDAC to CS hold time
GENERAL
t10
40
ns min
LDAC, CLR pulse width
1 All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and time from a voltage level of 1.6 V.
2 Rise and fall times should be no longer than 50 ns.
t 1
t3
t10
t 21
t 9
t4
LDAC
(SIMULTANEOUS
UPDATE)
LDAC
(PER-CHANNEL
UPDATE)
1ST
CLK
2ND
CLK
24TH
CLK
t5
t 8
t2
D23
D22
t 7
t 6
D1
D0
SCLK
DIN
MSB
LSB
FSYNC
01
00
6-
0
03
t12
t14
t17
t16
t15
t10
t18
t19
t11
t13
A0 A1 A2
CS
WR
DB0 TO DB13
LDAC
(SIMULTANEOUS
UPDATE)
LDAC
(PER-CHANNEL
UPDATE)
t20
BYSHF
01
00
6-
00
4
Figure 3. AD7834 Timing Diagram
Figure 4. AD7835 Timing Diagram
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