AD8310
Rev. F | Page 12 of 24
TOP-END
DETECTORS
COM
INHI
INLO
CP
CD
CM
COM
4k
Ω
~3k
Ω
125
Ω
6k
Ω
6k
Ω
2k
Ω
TYP 2.2V FOR
3V SUPPLY,
3.2V AT 5V
S
VPOS
IE
2.4mA
Q1
Q2
S
COMM
01084-024
2
5
8
1
Figure 24. Signal Input Interface
Occasionally, it might be desirable to use the dc-coupled
potential of the AD8310 in baseband applications. The main
challenge here is to present the signal at the elevated common-
mode input level, which might require the use of low noise, low
offset buffer amplifiers. In some cases, it might be possible to
use dual supplies of ±3 V, which allow the input pins to operate
at ground potential. The output, which is internally referenced
to the COMM pin (now at 3 V), can be positioned back to
ground level, with essentially no sensitivity to the particular
value of the negative supply.
OFFSET INTERFACE
The input-referred dc offsets in the signal path are nulled via
the interface associated with Pin 3, shown in
Figure 25. Q1
and Q2 are the first-stage input transistors, having slightly
unbalanced load resistors, resulting in a deliberate offset voltage
of about 1.5 mV referred to the input pins. Q3 generates a small
current to null this error, dependent on the voltage at the
OFLT pin. When Q1 and Q2 are perfectly matched, this voltage
is about 1.75 V. In practice, it can range from approximately
1 V to 2.5 V for an input-referred offset of ±1.5 mV.
48k
Ω
125
Ω
MAIN GAIN
STAGES
Q2
Q1
Q3
16
μA AT
BALANCE
Q4
gm
S
AVERAGE
ERROR
CURRENT
OFLT
TO LAST
DETECTOR
COFLT
33pF
COMM
VPOS
36k
Ω
INPUT
STAGE
BIAS,
01084-025
2
3
5
1.2V
Figure 25. Offset Interface and Offset-Nulling Path
In normal operation using an ac-coupled input signal, the
OFLT pin should be left unconnected. The gm cell, which is
gated off when the chip is disabled, converts a residual offset
(sensed at a point near the end of the cascade of amplifiers) to
a current. This is integrated by the on-chip capacitor, CHP, plus
any added external capacitance, COFLT, to generate the voltage
that is applied back to the input stage in the polarity needed to
null the output offset. From a small-signal perspective, this
feedback alters the response of the amplifier, which exhibits a
zero in its ac transfer function, resulting in a closed-loop, high-
pass 3 dB corner at about 2 MHz. An external capacitor lowers
the high-pass corner to arbitrarily low frequencies; using 1 μF,
the 3 dB corner is at 60 Hz.
OUTPUT INTERFACE
The nine detectors generate differential currents, having an
average value that is dependent on the signal input level, plus a
fluctuation at twice the input frequency. These are summed at
nodes LGP and LGN in
Figure 26. Further currents are added at
these nodes to position the intercept by slightly raising the
output for zero input and to provide temperature compensation.
0.2pF
3k
Ω
BIAS
1k
Ω
4k
Ω
4k
Ω
R1
3k
Ω
2
μA/dB
0.4pF
1.25k
Ω
1.25k
Ω
1.25k
Ω
1.25k
Ω
BFIN
0.4pF
60
μA
VPOS
COMM
BIAS
LGP
LGN
FROM ALL
DETECTORS
01084-026
2
6
5
VOUT
4
Figure 26. Simplified Output Interface