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參數(shù)資料
| 型號： | AD8310ARMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大小： | 0K |
| 描述： | IC AMP LOGARITHMIC 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 對數(shù)放大器 |
| 應(yīng)用： | 接收器信號強(qiáng)度指示（RSSI） |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 帶卷 (TR) |
AD8310
Rev. F | Page 14 of 24
USING THE AD8310
The AD8310 has very high gain and bandwidth. Consequently,
it is susceptible to all signals that appear at the input terminals
within a very broad frequency range. Without the benefit of
filtering, these are indistinguishable from the desired signal and
have the effect of raising the apparent noise floor (that is,
lowering the useful dynamic range). For example, while the
signal of interest has an IF of 50 MHz, any of the following can
easily be larger than the IF signal at the lower extremities of its
dynamic range: a few hundred mV of 60 Hz hum picked up due
to poor grounding techniques, spurious coupling from a digital
clock source on the same PC board, local radio stations, and so
on. Careful shielding and supply decoupling is, therefore,
essential. A ground plane should be used to provide a low
impedance connection to the common pin COMM, for the
decoupling capacitor(s) used at VPOS, and for the output
ground.
BASIC CONNECTIONS
Figure 27 shows the connections needed for most applications.
A supply voltage between 2.7 V and 5.5 V is applied to VPOS
and is decoupled using a 0.01 μF capacitor close to the pin.
Optionally, a small series resistor can be placed in the power
line to give additional filtering of power-supply noise. The
ENBL input, which has a threshold of approximately 1.3 V
(see Figure 15), should be tied to VPOS when this feature is not
needed.
VS
(2.7V–5.5V)
C2
0.01
μF
52.3
Ω
NC = NO CONNECT
C1
0.01
μF
C4
0.01
μF
NC
INHI ENBL
BFIN VPOS
INLO COMM OFLT VOUT
AD8310
4.7
Ω
OPTIONAL
VOUT (RSSI)
SIGNAL
INPUT
876
5
12
3
4
01084-027
Figure 27. Basic Connections
While the AD8310’s input can be driven differentially, the input
signal is, in general, single-ended. C1 is tied to ground, and the
input signal is coupled in through C2. Capacitor C1 and
Capacitor C2 should have the same value to minimize start-up
transients when the enable feature is used; otherwise, their
values need not be equal.
The 52.3 Ω resistor combines with the 1.1 kΩ input impedance
of the AD8310 to yield a simple broadband 50 Ω input match.
An input matching network can also be used (see the Input
Matching section).
The coupling time constant, 50 × CC/2, forms a high-pass corner
with a 3 dB attenuation at fHP = 1/(π × 50 × CC), where C1 =
C2 = CC. In high frequency applications, fHP should be as large
as possible to minimize the coupling of unwanted low frequency
signals. In low frequency applications, a simple RC network
forming a low-pass filter should be added at the input for similar
reasons. This should generally be placed at the generator side of
the coupling capacitors, thereby lowering the required capacitance
value for a given high-pass corner frequency.
For applications in which the ground plane might not be an equi-
potential (possibly due to noise in the ground plane), the low
input of an unbalanced source should generally be ac-coupled
through a separate connection of the low associated with the
source. Furthermore, it is good practice in such situations to
break the ground loop by inserting a small resistance to ground
in the low side of the input connector (see Figure 28).
VS
(2.7V–5.5V)
C2
0.01
μF
52.3
Ω
NC = NO CONNECT
C1
0.01
μF
C4
0.01
μF
NC
4.7
Ω
OPTIONAL
INHI ENBL BFIN VPOS
INLO COMM OFLT VOUT
AD8310
VOUT (RSSI)
SIGNAL
INPUT
4.7
Ω
GENERATOR
COMMON
BOARD-LEVEL
GROUND
01084-028
876
5
12
3
4
Figure 28. Connections for Isolation of Source Ground from Device Ground
Figure 29 shows the output vs. the input level for sine inputs at
10 MHz, 50 MHz, and 100 MHz. Figure 30 shows the logarith-
mic conformance under the same conditions.
INPUT LEVEL (dBV)
3.0
–120
–100
OUTPUT
(
V
)
–80
–60
–40
–20
0
(+13dBm)
20
2.5
2.0
1.5
1.0
0.5
0
10MHz
50MHz
100MHz
INTERCEPT
(–87dBm)
01084-029
Figure 29. Output vs. Input Level at 10 MHz, 50 MHz, and 100 MHz
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