參數(shù)資料
型號(hào): AD9257BCPZRL7-65
廠商: Analog Devices Inc
文件頁(yè)數(shù): 23/40頁(yè)
文件大?。?/td> 0K
描述: IC ADC 14BIT SRL 65MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 14
采樣率(每秒): 65M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 8
功率耗散(最大): 547mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 8 個(gè)差分
Data Sheet
AD9257
Rev. A | Page 3 of 40
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = 1.0 dBFS, unless otherwise noted.
Table 1.
Parameter1
Temp
AD9257-40
AD9257-65
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
14
Bits
ACCURACY
No Missing Codes
Full
Guaranteed
Offset Error
Full
0.6
0.3
+0.1
0.7
0.3
+0.1
% FSR
Offset Matching
Full
0
0.2
0.6
0
0.23
0.6
% FSR
Gain Error
Full
6.0
2.1
2.0
6.0
2.9
+1.0
% FSR
Gain Matching
Full
1.0
+1.7
+5.0
1.0
+1.6
+5.0
% FSR
Differential Nonlinearity (DNL)
Full
1.0
0.5/+0.8
+1.7
1.0
±0.6
+1.6
LSB
Integral Nonlinearity (INL)
Full
3.1
±1.1
+3.1
4.0
±1.1
+4.0
LSB
TEMPERATURE DRIFT
Offset Error
Full
±2
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Full
0.98
0.99
1.01
0.98
0.99
1.01
V
Load Regulation at 1.0 mA (VREF = 1 V)
Full
2
mV
Input Resistance
Full
7.5
k
INPUT-REFERRED NOISE
VREF = 1.0 V
25°C
0.91
0.94
LSB rms
ANALOG INPUTS
Differential Input Voltage (VREF = 1 V)
Full
2
V p-p
Common-Mode Voltage
Full
0.9
V
Common-Mode Range
Full
0.5
1.3
0.5
1.3
V
Differential Input Resistance
5.2
k
Differential Input Capacitance
Full
3.5
pF
POWER SUPPLY
AVDD
Full
1.7
1.8
1.9
1.7
1.8
1.9
V
DRVDD
Full
1.7
1.8
1.9
1.7
1.8
1.9
V
IAVDD
Full
147
156
198
211
mA
IDRVDD (ANSI-644 Mode)
Full
53
85
60
93
mA
IDRVDD (Reduced Range Mode)
25°C
38
45
mA
TOTAL POWER CONSUMPTION
Total Power Dissipation (Eight Channels, ANSI-644
Mode)
Full
360
434
464
547
mW
Total Power Dissipation (Eight Channels, Reduced
Range Mode)
25°C
333
437
mW
Power-Down Dissipation
25°C
1
mW
Standby Dissipation2
25°C
74
92
mW
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2
Can be controlled via the SPI.
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