參數(shù)資料
型號(hào): AD9511BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 23/60頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK DIST 5OUT PLL 48LFCSP
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 扇出緩沖器(分配),除法器
PLL:
輸入: 時(shí)鐘
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.2GHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 托盤(pán)
產(chǎn)品目錄頁(yè)面: 776 (CN2011-ZH PDF)
AD9511
Rev. A | Page 3 of 60
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to General Description .....................................................1
Changes to Table 1 and Table 2 .......................................................5
Changes to Table 4 ............................................................................7
Changes to Table 5 ............................................................................9
Changes to Table 6 ..........................................................................14
Changes to Table 8 and Table 9 .....................................................15
Changes to Table 11 ........................................................................16
Changes to Table 13 ........................................................................20
Changes to Figure 19 to Figure 23 ................................................24
Changes to Figure 30 and Figure 31 .............................................26
Changes to Figure 32 ......................................................................27
Changes to Figure 33 ......................................................................28
Changes to VCO/VCXO Clock Input—CLK2 Section ..............29
Changes to PLL Reference Divider—P Section...........................29
Changes to A and B Counters Section .........................................30
Changes to PLL Digital Lock Detect Section ..............................31
Changes to PLL Analog Lock Detect Section..............................32
Changes to Loss of Reference Section ..........................................32
Changes to FUNCTION Pin Section ...........................................32
Changes to RESETB: 58h<6:5> = 00b (Default) Section ...........32
Changes to SYNCB: 58h<6:5> = 01b Section..............................32
Changes to CLK1 and CLK2 Clock Inputs Section ....................33
Changes to Divider Phase Offset Section ....................................37
Changes to Individual Clock Output Power-Down Section .....39
Changes to Individual Circuit Block Power-Down Section......39
Changes to Soft Reset via the Serial Port Section .......................40
Changes to Multichip Synchronization Section..........................40
Changes to Serial Control Port Section .......................................41
Changes to Serial Control Port Pin Descriptions Section .........41
Changes to General Operation of Serial
Control Port Section .......................................................................41
Added Framing a Communication Cycle with CSB Section ....41
Added Communication Cycle—Instruction Plus
Data Section.....................................................................................41
Changes to Write Section...............................................................41
Changes to Read Section................................................................42
Changes to Instruction Word (16 Bits) Section ..........................42
Changes to Table 20 ........................................................................42
Changes to MSB/LSB First Transfers Section..............................42
Added Figure 52; Renumbered Sequentially...............................44
Changes to Table 23 ........................................................................45
Changes to Table 24 ........................................................................47
Changes to Power Supply...............................................................54
4/05—Revision 0: Initial Version
相關(guān)PDF資料
PDF描述
V110A48H300BL CONVERTER MOD DC/DC 48V 300W
VI-B60-MV CONVERTER MOD DC/DC 5V 150W
AD9518-2ABCPZ IC CLOCK GEN 6CH 2.2GHZ 48LFCSP
VI-B4Z-MV-B1 CONVERTER MOD DC/DC 2V 60W
VI-B3D-MW-B1 CONVERTER MOD DC/DC 85V 100W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9511BCPZ-REEL 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
AD9511BCPZ-REEL7 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器,PLL,頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS,LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP(7x7) 包裝:帶卷 (TR)
AD9511-VCO/PCB 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk
AD9512 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:800 MHz Clock Distribution IC,1.5 GHz Inputs, Dividers, Delay Adjust, Five Outputs
AD9512/PCB 制造商:Analog Devices 功能描述:Evaluation Kit For 1.2 GHZ Clock Distribution IC, 1.6 GHZ Inputs, Dividers, Delay Adjust, Five Outputs 制造商:Analog Devices 功能描述:EVAL KIT FOR 1.2 GHZ CLOCK DISTRIBUTION IC, 1.6 GHZ INPUTS, - Bulk