參數(shù)資料
型號: AD9511BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 24/60頁
文件大?。?/td> 0K
描述: IC CLOCK DIST 5OUT PLL 48LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 扇出緩沖器(分配),除法器
PLL:
輸入: 時鐘
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.2GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 776 (CN2011-ZH PDF)
AD9511
Rev. A | Page 30 of 60
Table 14. PLL Prescaler Modes
Mode
(FD = Fixed Divide
DM = Dual Modulus)
Value in 0Ah<4:2>
Divide By
FD
000
1
FD
001
2
P = 2 DM
010
P/P + 1 = 2/3
P = 4 DM
011
P/P + 1 = 4/5
P = 8 DM
100
P/P + 1 = 8/9
P = 16 DM
101
P/P + 1 = 16/17
P = 32 DM
110
P/P + 1 = 32/33
FD
111
3
When using the prescaler in FD mode, the A counter is not
used, and the B counter may need to be bypassed. The DM
prescaler modes set some upper limits on the frequency, which
can be applied to CLK2. See Table 15.
Table 15. Frequency Limits of Each Prescaler Mode
A and B Counters
The AD9511 B counter has a bypass mode (B = 1), which is not
available on the ADF4106. The B counter bypass mode is valid
only when using the prescaler in FD mode. The B counter is
bypassed by writing 1 to the B counter bypass bit (0Ah<6> =
1b). The valid range of the B counter is 3 to 8191. The default
after a reset is 0, which is invalid.
Note that the A counter is not used when the prescaler is in
FD mode.
Note also that the A/B counters have their own reset bit,
which is primarily intended for testing. The A and B counters
can also be reset using the R, A, and B counters’ shared reset bit
(09h<0>).
Determining Values for P, A, B, and R
When operating the AD9511 in a dual-modulus mode, the
input reference frequency, FREF, is related to the VCO output
frequency, FVCO.
FVCO = (FREF/R) × (PB + A) = FREF × N/R
When operating the prescaler in fixed divide mode, the A
counter is not used and the equation simplifies to
FVCO = (FREF/R) × (PB) = FREF × N/R
By using combinations of dual modulus and fixed divide
modes, the AD9511 can achieve values of N all the way down to
N = 1. Table 16 shows how a 10 MHz reference input may be
locked to any integer multiple of N. Note that the same value of
N may be derived in different ways, as illustrated by N = 12.
Table 16. P, A, B, R—Smallest Values for N
FREF
R
P
A
B
N
FVCO
Mode
Notes
10
1
X
1
10
FD
P = 1, B = 1 (Bypassed)
10
1
2
X
1
2
20
FD
P = 2, B = 1 (Bypassed)
10
1
X
3
30
FD
P = 1, B = 3
10
1
X
4
40
FD
P = 1, B = 4
10
1
X
5
50
FD
P = 1, B = 5
10
1
2
X
3
6
60
FD
P = 2, B = 3
10
1
2
0
3
6
60
DM
P/P + 1 = 2/3, A = 0, B = 3
10
1
2
1
3
7
70
DM
P/P + 1 = 2/3, A = 1, B = 3
10
1
2
3
8
80
DM
P/P + 1 = 2/3, A = 2, B = 3
10
1
2
1
4
9
90
DM
P/P + 1 = 2/3, A = 1, B = 4
10
1
2
X
5
10
100
FD
P = 2, B = 5
10
1
2
0
5
10
100
DM
P/P + 1 = 2/3, A = 0, B = 5
10
1
2
1
5
11
110
DM
P/P + 1 = 2/3, A = 1, B = 5
10
1
2
X
6
12
120
FD
P = 2, B = 6
10
1
2
0
6
12
120
DM
P/P + 1 = 2/3, A = 0, B = 6
10
1
4
0
3
12
120
DM
P/P + 1 = 4/5, A = 0, B = 3
10
1
4
1
3
13
130
DM
P/P + 1 = 4/5, A = 1, B = 3
Mode (DM = Dual Modulus)
CLK2
P = 2 DM (2/3)
<600 MHz
P = 4 DM (4/5)
<1000 MHz
P = 8 DM (8/9)
<1600 MHz
P = 16 DM
<1600 MHz
P = 32 DM
<1600 MHz
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