參數(shù)資料
型號(hào)： AD9511BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 51/60頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK DIST 5OUT PLL 48LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 扇出緩沖器（分配），除法器
PLL： 是
輸入： 時(shí)鐘
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:5
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.2GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
AD9511
Rev. A | Page 55 of 60
APPLICATIONS
USING THE AD9511 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer; any noise,
distortion, or timing jitter on the clock is combined with the
desired signal at the A/D output. Clock integrity requirements
scale with the analog input frequency and resolution, with
higher analog input frequency applications at ≥14-bit resolution
being the most stringent. The theoretical SNR of an ADC is
limited by the ADC resolution and the jitter on the sampling
clock. Considering an ideal ADC of infinite resolution where
the step size and quantization error can be ignored, the available
SNR can be expressed approximately by
×
=
j
ft
SNR
2π
1
log
20
where f is the highest analog frequency being digitized, and tj is
the rms jitter on the sampling clock. Figure 53 shows the
required sampling clock jitter as a function of the analog
frequency and effective number of bits (ENOB).
120
100
80
60
40
20
4
6
8
10
12
14
16
18
1
3
10
30
100
05286-024
FULL-SCALE SINE WAVE ANALOG INPUT FREQUENCY (MHz)
SNR
(dB)
ENOB
tj = 50fs
tj = 0.1ps
tj = 1ps
tj = 10ps
tj = 100ps
tj = 1ns
SNR = 20log10
1
2
πftj
Figure 53. ENOB and SNR vs. Analog Input Frequency
See Application Notes AN-756 and AN-501 on the ADI website
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection, which can
provide superior clock performance in a noisy environment.)
The AD9511 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
level, termination) should be considered when selecting the best
clocking/converter solution.
CMOS CLOCK DISTRIBUTION
The AD9511 provides two clock outputs (OUT3 and OUT4),
which are selectable as either CMOS or LVDS levels. When
selected as CMOS, these outputs provide for driving devices
requiring CMOS level logic at their clock inputs.
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be followed.
Point-to-point nets should be designed such that a driver has
one receiver only on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver. The
value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
preserve signal integrity.
05286-
096
10
Ω
MICROSTRIP
GND
50pF
60.4
Ω
1.0 INCH
CMOS
Figure 54. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9511 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 55. The far-
end termination network should match the PCB trace
impedance and provide the desired switching point. The
reduced signal swing can still meet receiver input requirements
in some applications. This may be useful when driving long
trace lengths on less critical nets.
05286-
097
50
Ω
10
Ω
OUT3, OUT4
SELECTED AS CMOS
VPULLUP = 3.3V
CMOS
3pF
100
Ω
100
Ω
Figure 55. CMOS Output with Far-End Termination
相關(guān)PDF資料
PDF描述
V110A48H300BL CONVERTER MOD DC/DC 48V 300W
VI-B60-MV CONVERTER MOD DC/DC 5V 150W
AD9518-2ABCPZ IC CLOCK GEN 6CH 2.2GHZ 48LFCSP
VI-B4Z-MV-B1 CONVERTER MOD DC/DC 2V 60W
VI-B3D-MW-B1 CONVERTER MOD DC/DC 85V 100W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9511BCPZ-REEL 制造商:AD 制造商全稱:Analog Devices 功能描述:1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
AD9511BCPZ-REEL7 功能描述:IC CLOCK DIST 5OUT PLL 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9511-VCO/PCB 制造商:Analog Devices 功能描述:EVAL BD FOR AD9511 1.2 GHZ CLOCK DISTRIBUTION IC, PLL CORE,D - Bulk
AD9512 制造商:AD 制造商全稱:Analog Devices 功能描述:800 MHz Clock Distribution IC,1.5 GHz Inputs, Dividers, Delay Adjust, Five Outputs
AD9512/PCB 制造商:Analog Devices 功能描述:Evaluation Kit For 1.2 GHZ Clock Distribution IC, 1.6 GHZ Inputs, Dividers, Delay Adjust, Five Outputs 制造商:Analog Devices 功能描述:EVAL KIT FOR 1.2 GHZ CLOCK DISTRIBUTION IC, 1.6 GHZ INPUTS, - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*