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參數(shù)資料
| 型號： | AD9516-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN W/PLL 64-LFCSP |
| 標準包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9516-5
Rev. A | Page 31 of 76
Note that the same value of N can be derived in different ways,
as illustrated by the case of N = 12. The user can choose a fixed
divide mode of P = 2 with B = 6; use the dual modulus mode of
2/3 with A = 0, B = 6; or use the dual modulus mode of 4/5 with
A = 0, B = 3.
A and B Counters
The B counter must be ≥3 or bypassed, and, unlike the R counter,
A = 0 is actually zero. When the prescaler is in dual modulus mode,
the A counter must be less than the B counter.
The maximum input frequency to the A or B counter is reflected
in the maximum prescaler output frequency (~300 MHz) that
is specified in Table 2. This is the prescaler input frequency
(external VCO or CLK) divided by P. For example, a dual
modulus mode of P = 8/9 mode is not allowed if the external
VCO frequency is greater than 2400 MHz because the frequency
going to the A or B counter is too high.
When the B counter is bypassed (B = 1), the A counter should
be set to 0, and the overall resulting divide is equal to the prescaler
setting, P. The possible divide ratios in this mode are 1, 2, 3, 4, 8,
16, and 32. This mode is useful only when an external VCO/VCXO
is used because the frequency range of the internal VCO requires
an overall feedback divider that is greater than 32.
Although manual reset is not normally required, the A and B
counters have their own reset bit. Alternatively, the A and B
counters can be reset using the shared reset bit of the R, A, and
B counters. Note that these reset bits are not self-clearing.
R, A, and B Counters—SYNC Pin Reset
The R, A, and B counters can also be reset simultaneously via
the SYNC pin. This function is controlled by Register 0x019[7:6]
(see
). The
SYNC pin reset is disabled by default.
R and N Divider Delays
Both the R and N dividers feature a programmable delay cell.
These delays can be enabled to allow adjustment of the phase
relationship between the PLL reference clock and the VCO or
CLK. Each delay is controlled by three bits. The total delay
range is about 1 ns. See Register 0x019 in Table 49.
LOCK DETECT
Digital Lock Detect (DLD)
By selecting the proper output through the mux on each pin, the
DLD function can be made available at the LD, STATUS, and
REFMON pins. The DLD circuit indicates a lock when the time
difference of the rising edges at the PFD inputs is less than a
specified value (the lock threshold). The loss of a lock is indicated
when the time difference exceeds a specified value (the unlock
threshold). Note that the unlock threshold is wider than the
lock threshold, which allows some phase error in excess of the
lock window to occur without chattering on the lock indicator.
The lock detect window timing depends on three settings: the
digital lock detect window bit (Register 0x018[4]), the antibacklash
pulse width setting (Register 0x017[1:0]), see Table 2), and the
lock detect counter (Register 0x018[6:5]). A lock is not indicated
until there is a programmable number of consecutive PFD cycles
with a time difference that is less than the lock detect threshold.
The lock detect circuit continues to indicate a lock until a time
difference greater than the unlock threshold occurs on a single
subsequent cycle. For the lock detect to work properly, the period
of the PFD frequency must be greater than the unlock threshold.
The number of consecutive PFD cycles required for lock is
programmable (Register 0x018[6:5]).
Analog Lock Detect (ALD)
The AD9516 provides an ALD function that can be selected for
use at the LD pin. There are two versions of ALD, as follows:
N-channel open-drain lock detect. This signal requires
a pull-up resistor to the positive supply, VS. The output is
normally high with short, low going pulses. Lock is indicated
by the minimum duty cycle of the low going pulses.
P-channel open-drain lock detect. This signal requires
a pull-down resistor to GND. The output is normally low
with short, high going pulses. Lock is indicated by the
minimum duty cycle of the high going pulses.
The analog lock detect function requires an R-C filter to
provide a logic level indicating lock/unlock.
AD9516-5
ALD
LD
R1
C
VOUT
R2
VS = 3.3V
079
72
-06
7
Figure 38. Example of Analog Lock Detect Filter, Using
N-Channel Open-Drain Driver
Current Source Digital Lock Detect (CSDLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is made possible by using
the current source lock detect function. This function is set
when it is selected as the output from the LD pin control
(Register 0x01A[5:0]).
The current source lock detect provides a current of 110 μA
when DLD is true, and it shorts to ground when DLD is false.
If a capacitor is connected to the LD pin, it charges at a rate that
is determined by the current source during the DLD true time
but is discharged nearly instantly when DLD is false. By
monitoring the voltage at the LD pin (top of the capacitor), it is
possible to get a logic high level only after the DLD has been
true for a sufficiently long time. Any momentary DLD false
resets the charging. By selecting a properly sized capacitor, it is
possible to delay a lock detect indication until the PLL is locked
in a stable condition and the lock detect does not chatter.
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