參數(shù)資料
型號(hào): AD9516-5BCPZ-REEL7
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 65/76頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK GEN W/PLL 64-LFCSP
標(biāo)準(zhǔn)包裝: 750
類(lèi)型: 時(shí)鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:14
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.4GHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
AD9516-5
Rev. A | Page 68 of 76
Table 54. LVDS/CMOS Channel Dividers
Reg.
Addr.
(Hex)
Bits
Name
Description
0x199
[7:4]
Low Cycles Divider 3.1
Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
[3:0]
High Cycles Divider 3.1
Number of clock cycles (minus 1) of the Divider 3.1 input during which the Divider 3.1 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
0x19A
[7:4]
Phase Offset Divider 3.2
Refers to LVDS/CMOS channel divider function description (default: 0x0).
[3:0]
Phase Offset Divider 3.1
Refers to LVDS/CMOS channel divider function description (default: 0x0).
0x19B
[7:4]
Low Cycles Divider 3.2
Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
[3:0]
High Cycles Divider 3.2
Number of clock cycles (minus 1) of the Divider 3.2 input during which the Divider 3.2 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
0x19C
5
Bypass Divider 3.2
Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output.
0: does not bypass (default).
1: bypasses.
4
Bypass Divider 3.1
Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output.
0: does not bypass (default).
1: bypasses.
3
Divider 3 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
2
Divider 3 force high
Forces Divider 3 output high. Requires that the Divider 3 nosync bit (Bit 3) also be set.
0: forces low (default).
1: forces high.
1
Start High Divider 3.2
Divider 3.2 starts high/low.
0: starts low (default).
1: starts high.
0
Start High Divider 3.1
Divider 3.1 starts high/low.
0: starts low (default).
1: starts high.
0x19D
0
Divider 3 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x19E
[7:4]
Low Cycles Divider 4.1
Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
[3:0]
High Cycles Divider 4.1
Number of clock cycles (minus 1) of the Divider 4.1 input during which the Divider 4.1 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x2).
0x19F
[7:4]
Phase Offset Divider 4.2
Refers to LVDSCMOS channel divider function description (default: 0x0).
[3:0]
Phase Offset Divider 4.1
Refers to LVDSCMOS channel divider function description (default: 0x0).
0x1A0
[7:4]
Low Cycles Divider 4.2
Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output
stays low. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
[3:0]
High Cycles Divider 4.2
Number of clock cycles (minus 1) of the Divider 4.2 input during which the Divider 4.2 output
stays high. A value of 0x7 means that the divider is low for eight input clock cycles (default: 0x1).
0x1A1
5
Bypass Divider 4.2
Bypasses (and powers down) 4.2 divider logic, routes clock to 4.2 output.
0: does not bypass (default).
1: bypasses.
4
Bypass Divider 4.1
Bypasses (and powers down) 4.1 divider logic, routes clock to 4.1 output.
0: does not bypass (default).
1: bypasses.
3
Divider 4 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
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