參數(shù)資料
型號(hào)： AD9516-5BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 70/76頁
文件大?。?/td> 0K
描述： IC CLOCK GEN W/PLL 64-LFCSP
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘發(fā)生器，扇出配送
PLL： 是
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:14
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.4GHz
除法器/乘法器： 是/無
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
AD9516-5
Rev. A | Page 72 of 76
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9516 provide the lowest jitter clock
signals that are available from the AD9516. The LVPECL outputs
(because they are open emitter) require a dc termination to bias
the output transistors. The simplified equivalent circuit in
Figure 47 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 59) or Y-termination (see Figure 60) is recommended.
In each case, the VS of the receiving buffer should match the
VS_LVPECL. If it does not match, ac coupling is recommended (see
The resistor network is designed to match the transmission line
impedance (50 Ω) and the switching threshold (VS 1.3 V).
VS_LVPECL
LVPECL
50
SINGLE-ENDED
(NOT COUPLED)
VS
VS_DRV
LVPECL
127
83
0
7972
-045
Figure 59. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
VS_LVPECL
LVPECL
Z0 = 50
VS = 3.3V
LVPECL
50
Z0 = 50
0
7972-
147
Figure 60. DC-Coupled 3.3 V LVPECL Y-Termination
VS_LVPECL
LVPECL
100 DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
VS
LVPECL
100
0.1nF
200
0
7
972-
04
6
Figure 61. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
shown in Figure 60, where VS_LVPECL = 2.5 V, the 50 Ω termination
resistor connected to ground should be changed to 19 Ω.
Thevenin-equivalent termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below VOL of the LVPECL
driver. In this case, VS_LVPECL on the AD9516 should equal VS of
the receiving buffer. Although the resistor combination shown
in Figure 60 results in a dc bias point of VS_LVPECL 2 V, the actual
common-mode voltage is VS_LVPECL 1.3 V because additional
current flows from the AD9516 LVPECL driver through the pull-
down resistor.
The circuit is identical when VS_LVPECL = 2.5 V, except that the
pull-down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.
LVDS CLOCK DISTRIBUTION
The AD9516 provides four clock outputs (OUT6 to OUT9) that
are selectable as either CMOS or LVDS level outputs. LVDS is a
differential output option that uses a current mode output stage.
The nominal current is 3.5 mA, which yields a 350 mV output
swing across a 100 Ω resistor. An output current of 7 mA is also
available in cases where a larger output swing is required. The
LVDS output meets or exceeds all ANSI/TIA/EIA-644
specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 62.
VS
LVDS
100
DIFFERENTIAL (COUPLED)
VS
LVDS
100
079
72-
047
Figure 62. LVDS Output Termination
See the AN-586 Application Note, LVDS Data Outputs for High-
Speed Analog-to-Digital Converters for more information on LVDS.
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