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參數(shù)資料
| 型號： | AD9516-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 29/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN W/PLL 64-LFCSP |
| 標準包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9516-5
Rev. A | Page 35 of 76
CLOCK DISTRIBUTION
A clock channel consists of a pair (or double pair, in the case of
CMOS) of outputs that share a common divider. A clock output
consists of the drivers that connect to the output pins. The clock
outputs have either LVPECL or LVDS/CMOS signal levels at
the pins.
The AD9516 has five clock channels: three channels are LVPECL
(six outputs); two channels are LVDS/CMOS (up to four LVDS
outputs, or up to eight CMOS outputs).
Each channel has its own programmable divider that divides the
clock frequency that is applied to its input. The LVPECL channel
dividers can divide by any integer from 2 to 32, or the divider
can be bypassed to achieve a divide-by-1. Each LVDS/CMOS
channel divider contains two of these divider blocks in a cascaded
configuration. The total division of the channel is the product
of the divide value of the cascaded dividers. This allows divide
values of (1 to 32) × (1 to 32), or up to 1024 (note that this is
not all values from 1 to 1024 but only the set of numbers that
are the product of the two dividers).
The VCO divider can be set to divide by 2, 3, 4, 5, or 6 and must
be used if the external clock signal connected to the CLK input
is greater than 1600 MHz.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 31 input clock cycles. The divider
outputs can also be set to start high or start low.
Operating Modes
There are two clock distribution operating modes. These operating
modes are shown in Table 25.
It is not necessary to use the VCO divider if the CLK frequency
is less than the maximum channel divider input frequency
(1600 MHz); otherwise, the VCO divider must be used to
reduce the frequency going to the channel dividers.
Table 25. Clock Distribution Operating Modes
Mode
0x1E1[0]
VCO Divider
2
0
Used
1
Not used
CLK Direct to LVPECL Outputs
It is possible to connect the CLK directly to the LVPECL outputs,
OUT0 to OUT5. However, the LVPECL outputs may not be able
to provide full a voltage swing at the highest frequencies.
To connect the LVPECL outputs directly to the CLK input, the
VCO divider must be selected as the source to the distribution
section even if no channel uses it.
Table 26. Settings for Routing VCO Divider Input Directly
to LVPECL Outputs
Register Setting
Selection
0x1E1[0] = 0b
VCO divider selected
0x192[1] = 1b
Direct to OUT0, OUT1 outputs
0x195[1] = 1b
Direct to OUT2, OUT3 outputs
0x198[1] = 1b
Direct to OUT4, OUT5 outputs
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (2, 3, 4, 5, and 6) and
how the frequency division for a channel is set. For the LVPECL
outputs, there is only one divider per channel. For the LVDS/
CMOS outputs, there are two dividers (X.1, X.2) cascaded
per channel.
Table 27. Frequency Division for Divider 0 to Divider 2
VCO
Divider
Setting
Channel
Divider
Setting
CLK Direct
to Output
Setting
Frequency
Division
2 to 6
Don’t care
Enable
1
2 to 6
Bypass
Disable
(2 to 6) × (1)
2 to 6
2 to 32
Disable
(2 to 6) × (2 to 32)
VCO Divider
Bypassed
Bypass
No
1
VCO Divider
Bypassed
2 to 32
No
2 to 32
Table 28. Frequency Division for Divider 3 and Divider 4
Channel Divider Setting
VCO Divider
Setting
X.1
X.2
Resulting Frequency
Division
2 to 6
Bypass
(2 to 6) × (1) × (1)
2 to 6
2 to 32
Bypass
(2 to 6) × (2 to 32) × (1)
2 to 6
2 to 32
(2 to 6) × (2 to 32) ×
(2 to 32)
Bypass
1
Bypass
2 to 32
1
(2 to 32) × (1)
Bypass
2 to 32
2 to 32 × (2 to 32)
The channel dividers feeding the LVPECL output drivers contain
one 2-to-32 frequency divider. This divider provides for division
by 2 to 32. Division by 1 is accomplished by bypassing the divider.
The dividers also provide for a programmable duty cycle, with
optional duty-cycle correction when the divide ratio is odd.
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