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參數(shù)資料
| 型號(hào)： | AD9516-5BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/76頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN W/PLL 64-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
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AD9516-5
Rev. A | Page 32 of 76
The voltage on the capacitor can be sensed by an external
comparator connected to the LD pin. However, there is an
internal LD pin comparator that can be read at the REFMON
pin control (Register 0x01B[4:0]) or the STATUS pin control
(Register 0x017[7:2]) as an active high signal. It is also available
as an active low signal (REFMON, Register 0x01B[4:0] and
STATUS, Register 0x017[7:2]). The internal LD pin comparator
trip point and hysteresis are listed in Table 12.
AD9516-5
LD
REFMON
OR
STATUS
C
VOUT
110A
DLD
LD PIN
COMPARATOR
07
97
2-
06
8
Figure 39. Current Source Lock Detect
External VCXO/VCO Clock Input (CLK/CLK)
CLK is a differential input that can be used to drive the AD9516
clock distribution section. This input can receive up to 2.4 GHz.
The pins are internally self-biased, and the input signal should
be ac-coupled via capacitors.
VS
CLOCK INPUT
STAGE
CLK
5k
2.5k
07
972-
03
2
Figure 40. CLK Equivalent Input Circuit
The CLK/CLK input can be used either as a distribution only
input (with the PLL off), or as a feedback input for an external
VCO/VCXO using the PLL. The CLK/CLK input can be used
for frequencies up to 2.4 GHz.
Holdover
The AD9516 PLL has a holdover function. Holdover is
implemented by putting the charge pump into a high impedance
state. This is useful when the PLL reference clock is lost. Holdover
mode allows the VCO to maintain a relatively constant frequency
even though there is no reference clock. Without this function,
the charge pump is placed into a constant pump-up or pump-
down state, resulting in a large VCO frequency shift. Because
the charge pump is placed in a high impedance state, any leakage
that occurs at the charge pump output or the VCO tuning node
causes a drift of the VCO frequency. This can be mitigated by
using a loop filter that contains a large capacitive component
because this drift is limited by the current leakage induced slew
rate (ILEAK/C) of the VCO control voltage. For most applications,
the frequency is sufficient for 3 sec to 5 sec.
Both a manual holdover mode, using the SYNC pin, and an
automatic holdover mode are provided. To use either function,
the holdover function must be enabled (Register 0x01D[0] and
Register 0x01D[2]).
Manual Holdover Mode
A manual holdover mode can be enabled that allows the user
to place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state, take the SYNC pin high. The charge pump then leaves the
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state as long as there is
no reference clock present.
The B counter (in the N divider) is reset synchronously with the
charge pump leaving the high impedance state on the reference
path PFD event. This helps align the edges out of the R and N
dividers for faster settling of the PLL. Because the prescaler is
not reset, this feature works best when the B and R numbers are
close because this results in a smaller phase difference for the
loop to settle out.
When using this mode, set the channel dividers to ignore the
SYNC pin (at least after an initial SYNC event). If the dividers are
not set to ignore the SYNC pin, the distribution outputs turn off
each time SYNC is taken low to put the part into holdover.
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| AD9517-0BCPZ | 制造商:Analog Devices 功能描述: |
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