參數(shù)資料
型號(hào)： AD9523/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/60頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9523
設(shè)計(jì)資源： AD9523(-1) Eval Board Schematic
AD9523(-1) BOM
AD9523(-1) Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9523
主要屬性： 板載 PLL 環(huán)路濾波器
次要屬性： LED 狀態(tài)指示器
已供物品： 板
相關(guān)產(chǎn)品： AD9523BCPZ-REEL7-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523BCPZ-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523-1BCPZ-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523-1BCPZ-REEL7-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523
Data Sheet
Rev. C | Page 24 of 60
CLOCK DISTRIBUTION
The clock distribution block provides an integrated solution for
generating multiple clock outputs based on frequency dividing
the PLL2 VCO divider output. The distribution output consists
of 14 channels (OUT0 to OUT13). Each of the output channels
has a dedicated divider and output driver, as shown in Figure 25.
The AD9523 also has the capability to route the VCXO output
to four of the outputs (OUT0 to OUT3).
Clock Dividers
The output clock distribution dividers are referred to as D0 to
D13, corresponding to output channels OUT0 through OUT13,
respectively. Each divider is programmable with 10 bits of division
depth that is equal to 1 to 1024. Dividers have duty cycle correction
to always give 50% duty cycle, even for odd divides.
Output Power-Down
Each of the output channels offers independent control of the
power-down functionality via the Channel 0 to Channel 13 control
registers (see Table 51). Each output channel has a dedicated
power-down bit for powering down the output driver. However,
if all 14 outputs are powered down, the entire distribution output
enters a deep sleep mode. Although each channel has a channel
power-down control signal, it may sometimes be desirable to
power down an output driver while maintaining the divider’s
synchronization with the other channel dividers. This is accom-
plished by placing the output in tristate mode (this works in
CMOS mode, as well).
Multimode Output Drivers
The user has independent control of the operating mode of each of
the fourteen output channels via the Channel 0 to Channel 13
control registers (see Table 51). The operating mode control
includes the following:
Logic family and pin functionality
Output drive strength
Output polarity
The four least significant bits (LSBs) of each of the 14 Channel 0
to Channel 13 control registers comprise the driver mode bits. The
mode value selects the desired logic family and pin functionality
of an output channel, as listed in Table 51. This driver design
allows a common 100 external resistor for all the different
driver modes of operation that are illustrated in Figure 26.
If the output channel is ac-coupled to the circuit to be clocked,
changing the mode varies the voltage swing to determine sensi-
tivity to the drive level. For example, in LVDS mode, a current of
3.5 mA causes a 350 mV peak voltage. Likewise, in LVPECL mode,
a current of 8 mA causes an 800 mV peak voltage at the 100 load
resistor. Using any termination other than those specified in the
results in damage or decrease end of life performance
In addition to the four mode bits, each of the 14 Channel 0 to
Channel 13 control registers includes the following control bits:
Invert divider output. Enables the user to choose between
normal polarity and inverted polarity. Normal polarity is the
default state. Inverted polarity reverses the representation of
Logic 0 and Logic 1, regardless of the logic family.
Ignore sync. Makes the divider ignore the SYNC signal
from any source.
Power-down channel. Powers down the entire channel.
Lower power mode.
Driver mode.
Channel divider.
Divider phase.
3.5mA/8mA
LVDS/LVPECL
ENABLED
HSTL
ENABLED
HSTL
ENABLED
50
P
N
P
100 LOAD
CM
VDD3_OUT[x:y]
1.25V LVDS
VDD – 1.3V LVPECL
CM
COMMON-MODE
CIRCUIT
+
–
08439-
031
Figure 26. Multimode Driver
Clock Distribution Synchronization
A block diagram of the clock distribution synchronization
functionality is shown in Figure 27. The synchronization
sequence begins with the primary synchronization signal,
which ultimately results in delivery of a synchronization strobe
to the clock distribution logic.
As indicated, the primary synchronization signal originates
from one of the following sources:
Direct synchronization source via the sync dividers bit (see
Register 0x232, Bit 0 in Table 55)
Device pin, SYNC (Pin 17)
An automatic synchronization of the divider is initiated the first
time that PLL2 locks after a power-up or reset event. Subsequent
lock/unlock events do not initiate a resynchronization of the
distribution dividers unless they are preceded by a power-down
or reset of the part. Both sources of the primary synchronization
signal are logic OR’d; therefore, any one of them can synchronize
the clock distribution output at any time.
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