參數(shù)資料
型號(hào): AD9523/PCBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 37/60頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9523
設(shè)計(jì)資源: AD9523(-1) Eval Board Schematic
AD9523(-1) BOM
AD9523(-1) Gerber Files
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9523
主要屬性: 板載 PLL 環(huán)路濾波器
次要屬性: LED 狀態(tài)指示器
已供物品:
相關(guān)產(chǎn)品: AD9523BCPZ-REEL7-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523BCPZ-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523-1BCPZ-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523-1BCPZ-REEL7-ND - IC INTEGER-N CLCK GEN 72LFCSP
AD9523
Data Sheet
Rev. C | Page 42 of 60
Addr
(Hex)
Register
Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
0x1A2
Channel 6
control
Invert
divider
output
Ignore
sync
Power-
down
channel
Lower power
mode
Driver mode
0x00
0x1A3
10-bit channel divider[7:0] (LSB)
0x1F
0x1A4
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1A5
Channel 7
control
Invert
divider
output
Ignore
sync
Power-
down
channel
Lower power
mode
Driver mode
0x20
0x1A6
10-bit channel divider[7:0] (LSB)
0x1F
0x1A7
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1A8
Channel 8
control
Invert
divider
output
Ignore
sync
Power-
down
channel
Lower power
mode
Driver mode
0x00
0x1A9
10-bit channel divider[7:0] (LSB)
0x1F
0x1AA
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1AB
Channel 9
control
Invert
divider
output
Ignore
sync
Power-
down
channel
Lower power
mode
Driver mode
0x20
0x1AC
10-bit channel divider[7:0] (LSB)
0x1F
0x1AD
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1AE
Channel 10
control
Invert
divider
output
Ignore
sync
Power-
down
channel
Lower power
mode
Driver mode
0x00
0x1AF
10-bit channel divider[7:0] (LSB)
0x1F
0x1B0
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1B1
Channel 11
control
Invert
divider
output
Ignore
sync
Power-
down
channel
Lower power
mode
Driver mode
0x20
0x1B2
10-bit channel divider[7:0] (LSB)
0x1F
0x1B3
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1B4
Channel 12
control
Invert
divider
output
Ignore
sync
Power-
down
channel
Lower power
mode
Driver mode
0x00
0x1B5
10-bit channel divider[7:0] (LSB)
0x1F
0x1B6
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1B7
Channel 13
control
Invert
divider
output
Ignore
sync
Power-
down
channel
Lower power
mode
Driver mode
0x20
0x1B8
10-bit channel divider[7:0] (LSB)
0x1F
0x1B9
Divider phase[5:0]
10-bit channel divider[9:8] (MSB)
0x04
0x1BA
PLL1 output
control
Reserved
PLL1 output
CMOS driver
strength
Out PLL1 output
0x00
0x1BB
PLL1 output
channel
control
PLL1
output
driver
power-
down
Reserved
Route
VCXO
clock to
Ch 3
divider
input
Route
VCXO
clock to
Ch 2
divider
input
Route VCXO
clock to Ch 1
divider input
Route VCXO
clock to Ch 0
divider input
0x80
Readback
0x22C
Readback 0
Status
PLL2
reference
clock
Status
PLL1
feedback
clock
Status
VCXO
Status
REF_TEST
Status
REFB
Status
REFA
Lock detect
PLL2
Lock detect
PLL1
0x22D
Readback 1
Reserved
Holdover
active
Selected
reference
(in auto
mode)
Reserved
VCO
calibration
in progress
0x22E
Readback 2
Reserved
0x22F
Readback 3
Reserved
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