參數(shù)資料
型號(hào)： AD9524BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/56頁(yè)
文件大小： 0K
描述： IC INTEGER-N CLCK GEN 48LFCSP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配）
PLL： 是
主要目的： 以太網(wǎng)，光纖通道，SONET/SDH
輸入： CMOS
輸出： HSTL，LVCMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:6
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1GHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 標(biāo)準(zhǔn)包裝
配用： AD9524BCPZ-ND - IC INTEGER-N CLCK GEN 48LFCSP
其它名稱(chēng)： AD9524BCPZ-REEL7DKR
Data Sheet
AD9524
Rev. E | Page 13 of 56
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
2
4
2
3
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
4
5
4
6
4
7
4
8
4
3
4
2
4
1
4
0
3
9
3
8
3
7
TOP VIEW
(Not to Scale)
AD9524
25
26
27
28
29
30
31
32
33
34
35
36
8
9
10
11
12
0
908
1-
0
02
REFA
REFB
LF1_EXT_CAP
OSC_CTRL
OSC_IN
LF2_EXT_CAP
LDO_PLL2
VDD3_PLL2
LDO_VCO
SYN
C
V
DD3
_RE
F
CS
SC
L
K
/SC
L
S
D
IO
/S
D
A
SD
O
OU
T
5
OU
T
5
V
DD3
_O
UT
[4
:5
]
OU
T
4
OU
T
4
V
D
1
.8
_
O
U
T
[4
:5
]
VDD1.8_OUT[2:3]
OUT2
VDD3_OUT[2:3]
OUT3
EEPROM_SEL
PD
RESET
REF_TEST
P
L
1_O
UT
LD
O_
P
L
1
V
DD3
_P
L
1
RE
F
_
S
E
L
ZD
_
IN
ZD
_
IN
V
DD1
.8
_
O
UT
[0
:1
]
OU
T0
OU
T0
V
DD3
_O
UT
[0
:1
]
OU
T1
OU
T1
STATUS0/SP0
STATUS1/SP1
NOTES
1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND.
AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT.
ON EXISTING PCB DESIGNS, IT ISACCEPTABLE TO LEAVE PIN 42 CONNECTED TO 1.8V SUPPLY.
2. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE
SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY
AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 2. Pin Configuration
Table 19. Pin Function Descriptions
Pin
No.
Mnemonic
Type1
Description
1
REFA
I
Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
2
REFA
I
Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for
the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input.
3
REFB
I
Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
4
REFB
I
Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for
the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
5
LF1_EXT_CAP
O
PLL1 External Loop Filter Capacitor. Connect a loop filter capacitor to this pin and to ground.
6
OSC_CTRL
O
Oscillator Control Voltage. Connect this pinto the voltage control pin of the external oscillator.
7
OSC_IN
I
PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the PLL reference.
Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
8
OSC_IN
I
Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the
PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.
9
LF2_EXT_CAP
O
PLL2 External Loop Filter Capacitor Connection. Connect a capacitor to this pin and LDO_VCO.
10
LDO_PLL2
P/O
LDO Decoupling Pin for PLL2 1.8 V Internal Regulator. Connect a 0.47 μF decoupling capacitor
from this pin to ground. Note that for best performance, the LDO bypass capacitor must be
placed in close proximity to the device.
11
VDD3_PLL2
P
3.3 V Supply for PLL2.
12
LDO_VCO
P/O
2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 μF decoupling capacitor
from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be
placed in close proximity to the device.
13
SYNC
I
Manual Synchronization. This pin initiates a manual synchronization and has an internal
40 kΩ pull-up resistor.
14
VDD3_REF
P
3.3 V Supply for Output Clock Drivers Reference.
15
CS
I
Serial Control Port Chip Select, Active Low. This pin has an internal 40 kΩ pull-up resistor.
16
SCLK/SCL
I
Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). Data clock for serial programming.
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