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參數(shù)資料
| 型號(hào)： | AD9524BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 50/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTEGER-N CLCK GEN 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配） |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，光纖通道，SONET/SDH |
| 輸入： | CMOS |
| 輸出： | HSTL，LVCMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 配用： | AD9524BCPZ-ND - IC INTEGER-N CLCK GEN 48LFCSP |
| 其它名稱： | AD9524BCPZ-REEL7DKR |
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AD9524
Data Sheet
Rev. E | Page 54 of 56
Table 57. Power-Down Control
Address
Bits
Bit Name
Description
0x233
[7:3]
Reserved
Reserved.
2
PLL1 power-down
1: power-down (default).
0: normal operation.
1
PLL2 power-down
1: power-down (default).
0: normal operation.
0
Distribution power-
down
Powers down the distribution.
1: power-down (default).
0: normal operation.
Table 58. Update All Registers
Address
Bits
Bit Name
Description
0x234
[7:1]
Reserved
Reserved.
0
IO_Update
This bit must be set to 1 to transfer the contents of the buffer registers into the active registers,
which happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to
be set back to 0.
1 (self-clearing): update all active registers to the contents of the buffer registers.
EEPROM Buffer (Address 0xA00 to Address 0xA16)
Table 59. EEPROM Buffer Segment
Address
Bits
Bit Name
Description
0xA00
to
0xA16
[7:0]
EEPROM Buffer
Segment Register 1 to
EEPROM Buffer
Segment Register 23
The EEPROM buffer segment section stores the starting address and number of bytes that are to
be stored and read back to and from the EEPROM. Because the register space is noncontiguous,
the EEPROM controller needs to know the starting address and number of bytes in the register
space to store and retrieve from the EEPROM. In addition, there are special instructions for the
EEPROM controller: operational codes (that is, IO_Update and end-of-data) that are also stored
in the EEPROM buffer segment. The on-chip default setting of the EEPROM buffer segment
registers is designed such that all registers are transferred to/from the EEPROM, and an
IO_Update is issued after the transfer (see the Programming the EEPROM Buffer Segment section).
EEPROM Control (Address 0xB00 to Address 0xB03)
Table 60. Status_EEPROM
Address
Bits
Bit Name
Description
0xB00
[7:1]
Reserved
Reserved.
0
Status_EEPROM
(read only)
This read-only bit indicates the status of the data transferred between the EEPROM and the
buffer register bank during the writing and reading of the EEPROM. This signal is also available
at the STATUS0 pin when Register 0x232, Bit 4 is set.
0: data transfer is complete.
1: data transfer is not complete.
Table 61. EEPROM Error Checking Readback
Address
Bits
Bit Name
Description
0xB01
[7:1]
Reserved
Reserved.
0
EEPROM data error
(read only)
This read-only bit indicates an error during the data transfer between the EEPROM and the buffer.
0: no error; data is correct.
1: incorrect data detected.
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