參數(shù)資料
型號(hào): AD9524BCPZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 17/56頁(yè)
文件大?。?/td> 0K
描述: IC INTEGER-N CLCK GEN 48LFCSP
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 時(shí)鐘/頻率發(fā)生器,扇出緩沖器(分配)
PLL:
主要目的: 以太網(wǎng),光纖通道,SONET/SDH
輸入: CMOS
輸出: HSTL,LVCMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:6
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1GHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 標(biāo)準(zhǔn)包裝
配用: AD9524BCPZ-ND - IC INTEGER-N CLCK GEN 48LFCSP
其它名稱(chēng): AD9524BCPZ-REEL7DKR
AD9524
Data Sheet
Rev. E | Page 24 of 56
Clock Distribution Synchronization
A block diagram of the clock distribution synchronization
functionality is shown in Figure 27. The synchronization
sequence begins with the primary synchronization signal,
which ultimately results in delivery of a synchronization strobe
to the clock distribution logic.
As indicated, the primary synchronization signal originates
from one of the following sources:
Direct synchronization source via the sync dividers bit (see
Register 0x232, Bit 0 in Table 56)
Device pin, SYNC (Pin 13)
An automatic synchronization of the divider is initiated the first
time that PLL2 locks after a power-up or reset event. Subsequent
lock/unlock events do not initiate a resynchronization of the
distribution dividers unless they are preceded by a power-down
or reset of the part.
FAN OUT
VCO OUTPUT DIVIDER
SYNC (PIN 13)
SYNC
DIVIDER
DRIVER
OUTx
OUT
SYNC
PHASE
DIVIDE
SYNC DIVIDERS BIT
09081-
025
Figure 27. Clock Output Synchronization Block Diagram
DIVIDE = 2, PHASE = 0
DIVIDE = 2, PHASE = 6
VCO DIVIDER OUTPUT CLOCK
SYNC
CONTROL
6 × 0.5 PERIODS
0
84
39-
0
26
Figure 28. Clock Output Synchronization Timing Diagram
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