FIN = " />
參數(shù)資料
型號: AD9540/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 28/32頁
文件大?。?/td> 0K
描述: BOARD EVAL CLK GEN SYNTH 48LFCSP
設(shè)計(jì)資源: AD9540 Eval Brd Schematics
AD9540 Eval Brd BOM
AD9540 Gerber Files
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
已用 IC / 零件: AD9540
已供物品:
AD9540
Rev. A | Page 5 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
FIN = 1966.08 MHz, FOUT = 491.52 MHz
RF Divider R = 4
@ 10 Hz
105
dBc/Hz
@ 100 Hz
112
dBc/Hz
@ 1 kHz
122
dBc/Hz
@ 10 kHz
130
dBc/Hz
@ 100 kHz
141
dBc/Hz
@ 1 MHz
144
dBc/Hz
>3 MHz
146
dBc/Hz
FIN = 2488 MHz, FOUT = 622 MHz
RF Divider R = 4
@ 10 Hz
100
dBc/Hz
@ 100 Hz
108
dBc/Hz
@ 1 kHz
115
dBc/Hz
@ 10 kHz
125
dBc/Hz
@ 100 kHz
135
dBc/Hz
@ 1 MHz
140
dBc/Hz
≥3 MHz
142
dBc/Hz
PHASE FREQUENCY DETECTOR/CHARGE PUMP
REFIN Input
Input Frequency2
÷M Set to Divide by at Least 4
655
MHz
÷M Bypassed
200
MHz
Input Voltage Levels
200
450
600
mV p-p
Input Capacitance
10
pF
Input Resistance
1500
CLK2 Input
Input Frequency
÷N Set to Divide by at Least 4
655
MHz
÷N Bypassed
200
MHz
Input Voltage Levels
200
450
600
mV p-p
Input Capacitance
10
pF
Input Resistance
1500
Charge Pump Source/Sink Maximum Current
4
mA
Charge Pump Source/Sink Accuracy
5
%
Charge Pump Source/Sink Matching
2
%
Charge Pump Output Compliance Range3
0.5
CP_VDD 0.5
V
STATUS Drive Strength
2
mA
PHASE FREQUENCY DETECTOR NOISE FLOOR
@ 50 kHz PFD Frequency
148
dBc/Hz
@ 2 MHz PFD Frequency
133
dBc/Hz
@ 100 MHz PFD Frequency
116
dBc/Hz
@ 200 MHz PFD Frequency
113
dBc/Hz
RF DIVIDER (CLK1 ) INPUT SECTION (÷R)
RF Divider Input Range
1
2700
MHz
DDS SYSCLK not to
exceed 400 MSPS
Input Capacitance (DC)
3
pF
Input Impedance (DC)
1500
Input Duty Cycle
42
50
58
%
Input Power/Sensitivity
10
+4
dBm
Single-ended, into a 50 load4
Input Voltage Level
200
1000
mV p-p
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