51.84 MHz FOUT @ 10 Hz" />
參數(shù)資料
型號(hào)： AD9540/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 31/32頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL CLK GEN SYNTH 48LFCSP
設(shè)計(jì)資源： AD9540 Eval Brd Schematics
AD9540 Eval Brd BOM
AD9540 Gerber Files
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
已用 IC / 零件： AD9540
已供物品： 板
AD9540
Rev. A | Page 8 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
51.84 MHz FOUT
@ 10 Hz Offset
110
dBc/Hz
@ 100 Hz Offset
121
dBc/Hz
@ 1 kHz Offset
135
dBc/Hz
@ 10 kHz Offset
142
dBc/Hz
@ 100 kHz Offset
148
dBc/Hz
> 1 MHz Offset
153
dBc/Hz
105 MHz Analog Out
@ 10 Hz Offset
105
dBc/Hz
@ 100 Hz Offset
115
dBc/Hz
@ 1 kHz Offset
126
dBc/Hz
@ 10 kHz Offset
132
dBc/Hz
@ 100 kHz Offset
140
dBc/Hz
>1 MHz Offset
145
dBc/Hz
155.52 MHz Analog Out
@ 10 Hz Offset
100
dBc/Hz
@ 100 Hz Offset
112
dBc/Hz
@ 1 kHz Offset
123
dBc/Hz
@ 10 kHz Offset
131
dBc/Hz
@ 100 kHz Offset
138
dBc/Hz
>1 MHz Offset
144
dBc/Hz
1 The SNR of a 14-bit ADC was measured with an ENCODE rate of 105 MSPS and an AIN of 170 MHz. The resultant SNR was known to be limited by the jitter of the clock,
not by the noise on the AIN signal. From this SNR value, the jitter affecting the measurement can be back calculated.
2 Driving the REFIN input buffer. The crystal oscillator section of this input stage performs up to only 30 MHz.
3 The charge pump output compliance range is functionally 0.2 V to (CP_VDD 0.2 V). The value listed here is the compliance range for 5% matching.
4 The input impedance of the CLK1 input is 1500 . However, to provide matching on the clock line, an external 50 load is used.
5 Measured as peak-to-peak between DAC outputs.
6 For a 4.02 k resistor from DRV_RSET to GND.
7 Assumes a 1 mA load.
LOOP MEASUREMENT CONDITIONS
622 MHz OC-12 Clock
VCO = Sirenza 190-640T
Reference = Wenzel 500-10116 (30.3 MHz)
Loop Filter = 10 kHz BW, 60° Phase Margin
C1 = 170 nF, R1 = 14.4 , C2 = 5.11 F, R2 = 89.3 ,
C3 Omitted
CP_OUT = 4 mA (Scaler = ×8)
÷R = 2, ÷M = 1, ÷N = 1
105 MHz Converter Clock
VCO = Sirenza 190-845T
Reference = Wenzel 500-10116 (30.3 MHz)
Loop Filter = 10 kHz BW, 45° Phase Margin
C1 = 117 nF, R1 = 28 , C2 = 1.6 F, R2 = 57.1 , C3 = 53.4 nF
CP_OUT = 4 mA (Scaler = ×8)
÷R = 8, ÷M = 1, ÷N = 1
C1
C3
INPUT
OUTPUT
C2
R1
R2
04947-
041
Figure 2. Generic Loop Filter
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