參數(shù)資料
型號(hào): AD9540/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 3/32頁
文件大?。?/td> 0K
描述: BOARD EVAL CLK GEN SYNTH 48LFCSP
設(shè)計(jì)資源: AD9540 Eval Brd Schematics
AD9540 Eval Brd BOM
AD9540 Gerber Files
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
已用 IC / 零件: AD9540
已供物品:
AD9540
Rev. A | Page 11 of 32
Pin No.
Mnemonic
Description
21, 22, 23
S0, S1, S2
Clock Frequency and Delay Select Pins. These pins specify one of eight clock frequency/delay
profiles.
28
CLK1
RF Divider and Internal Clock Complementary Input.
29
CLK1
RF Divider and Internal Clock Input.
31, 35
CP_VDD
Charge Pump and CML Driver Supply Pin. 3.3 V analog (clean) supply.
32
OUT0
CML Driver Complementary Output.
33
OUT0
CML Driver Output.
36
CP_OUT
Charge Pump Output.
39
REFIN
Phase Frequency Detector Reference Input.
40
REFIN
Phase Frequency Detector Reference Complementary Input.
41
CLK2
Phase Frequency Detector Oscillator (Feedback) Complementary Input.
42
CLK2
Phase Frequency Detector Oscillator (Feedback) Input.
45
CP_RSET
Charge Pump Current Set. Program charge pump current with a resistor to AGND.
46
DRV_RSET
CML Driver Output Current Set. Program CML output current with a resistor to AGND.
47
DAC_RSET
DAC Output Current Set. Program DAC output current with a resistor to AGND.
Paddle
Exposed Paddle
The exposed paddle on this package is an electrical connection as well as a thermal enhancement.
In order for the device to function properly, the paddle must be attached to analog ground.
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