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參數(shù)資料
| 型號： | AD9548/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9548 |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 設計資源： | AD9548 Schematic AD9548 BOM AD9548 Eval Brd Layers |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9548 |
| 主要屬性： | 62.5 ~ 450 MHz 輸出頻率 |
| 次要屬性： | SPI 和 I2C 兼容控制端口 |
| 已供物品： | 板 |
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Data Sheet
AD9548
Rev. E | Page 17 of 112
Pin No.
Mnemonic
Input/
Output
Pin Type
Description
53
SYSCLKP
I
Differential
input
System Clock Input. SYSCLKP contains internal dc biasing and should be ac-
coupled with a 0.01 μF capacitor, except when using a crystal, in which case
connect the crystal across SYSCLKP and SYSCLKN. Single-ended 1.8 V CMOS is
also an option but can introduce a spur if the doubler is enabled and the duty
cycle is not 50%. When using SYSCLKP as a single-ended input, connect a 0.01 μF
capacitor from SYSCLKN to ground.
56, 75
NC
I
No Connection. These pins should be left floating.
59
AVDD
I
Power
1.8 V Analog Power Supply.
57, 58
TDC_VRB,
TDC_VRT
I
Use capacitive decoupling on these pins (see Figure 39).
60, 66, 67,
73
AVDD3
I
Power
3.3 V Analog (Reference Input) Power Supply.
61
REFA
I
Differential
input
Reference A Input. This internally biased input is typically ac-coupled and, when
configured as such, can accept any differential signal with single-ended swing up
to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.
62
REFAA
I
Differential
input
Complementary Reference A Input. Complementary signal to the input provided
on Pin 61. The user can configure this pin as a separate single-ended input.
63, 70, 74
AVDD
I
Power
1.8 V Analog (Reference Input) Power Supply.
64
REFB
I
Differential
input
Reference B Input. This internally biased input is typically ac-coupled and, when
configured as such, can accept any differential signal with single-ended swing up
to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.
65
REFBB
I
Differential
input
Complementary Reference B Input. Complementary signal to the input provided
on Pin 64. The user can configure this pin as a separate single-ended input.
68
REFC
I
Differential
input
Reference C Input. This internally biased input is typically ac-coupled and, when
configured as such, can accept any differential signal with single-ended swing up
to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.
69
REFCC
I
Differential
input
Complementary Reference C Input. Complementary signal to the input provided
on Pin 68. The user can configure this pin as a separate single-ended input.
71
REFD
I
Differential
input
Reference D Input. This internally biased input is typically ac-coupled and, when
configured as such, can accept any differential signal with single-ended swing up
to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.
72
REFDD
I
Differential
input
Complementary Reference D Input. Complementary signal to the input provided
on Pin 71. The user can configure this pin as a separate single-ended input.
76
IRQ
O
Logic
Interrupt Request Line.
78, 79, 80,
81, 84, 85,
86, 87
M0, M1, M2,
M3, M4, M5,
M6, M7
I/O
3.3 V CMOS
Configurable I/O Pins. These pins are configured under program control.
EP
VSS
O
Exposed
pad
The exposed pad must be connected to ground (VSS).
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