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參數(shù)資料
| 型號： | AD9548/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9548 |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 設計資源： | AD9548 Schematic AD9548 BOM AD9548 Eval Brd Layers |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9548 |
| 主要屬性： | 62.5 ~ 450 MHz 輸出頻率 |
| 次要屬性： | SPI 和 I2C 兼容控制端口 |
| 已供物品： | 板 |
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AD9548
Data Sheet
Rev. E | Page 102 of 112
NONVOLATILE MEMORY (EEPROM) CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E03)
Table 142. EEPROM Control
Address
Bits
Bit Name
Description
0x0E00
[7:2]
Unused
[1]
Half rate mode
EEPROM serial communication rate.
0 (default) = 400 kHz (normal).
1 = 200 kHz.
[0]
Write enable
EEPROM write enable/protect.
0 (default) = EEPROM write protected.
1 = EEPROM write enabled.
0x0E01
[7:5]
Unused
[4:0]
Condition value
When set to a nonzero value (default = 0), these bits establish the condition for
EEPROM downloads.
0x0E02
[7:1]
Unused
[0]
Save to EEPROM
Upload data to the EEPROM based on the EEPROM storage sequence. This is an
autoclearing bit. When an EEPROM save/load transfer is complete, wait a minimum of
10 μs before starting the next EEPROM save/load transfer.
0x0E03
[7:2]
Unused
[1]
Load from EEPROM
Download data from the EEPROM. This is an autoclearing bit. When an EEPROM
save/load transfer is complete, wait a minimum of 10 μs before starting the next
EEPROM save/load transfer.
[0]
Unused
EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3F)
The default settings of Register 0x0E10 to Register 0x0E33 embody a sample scratch pad instruction sequence. The following is a
description of the register defaults under the assumption that the controller has been instructed to carry out an EEPROM storage
sequence.
Table 143. EEPROM Storage Sequence for System Clock Settings
Address
Bits
Bit Name
Description
0x0E10
[7:0]
System clock
The default value of this register is 0x08, which the controller interprets as a data
instruction. Its decimal value is 8, which tells the controller to transfer nine bytes of
data (8 + 1) beginning at the address specified by the next two bytes. The
controller stores 0x08 in the EEPROM and increments the EEPROM address pointer.
0x0E11
[7:0]
System clock
The default value of these two registers is 0x0100. Note that Register 0x0E11 and
Register 0x0E12 are the most significant and least significant bytes of the target
address, respectively. Because the previous register contains a data instruction,
these two registers define a starting address (in this case, 0x0100). The controller
stores 0x0100 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers nine bytes from the register map (beginning at Address 0x0100) to the
EEPROM and increments the EEPROM address pointer by 10 (nine data bytes and
one checksum byte). The nine bytes transferred correspond to the system clock
parameters in the register map.
0x0E12
[7:0]
0x0E13
[7:0]
I/O update
The default value of this register is 0x80, which the controller interprets as an I/O
update instruction. The controller stores 0x80 in the EEPROM and increments the
EEPROM address pointer.
Table 144. EEPROM Storage Sequence for System Clock Calibration
Address
Bits
Bit Name
Description
0x0E14
[7:0]
SYSCLK calibrate
The default value of this register is 0xA0, which the controller interprets as a
calibrate instruction. The controller stores 0xA0 in the EEPROM and increments the
EEPROM address pointer.
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