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參數(shù)資料
| 型號： | AD9548/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/112頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9548 |
| 產(chǎn)品變化通告： | AD9548 Mask Change 20/Oct/2010 |
| 設(shè)計資源： | AD9548 Schematic AD9548 BOM AD9548 Eval Brd Layers |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9548 |
| 主要屬性： | 62.5 ~ 450 MHz 輸出頻率 |
| 次要屬性： | SPI 和 I2C 兼容控制端口 |
| 已供物品： | 板 |
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AD9548
Data Sheet
Rev. E | Page 26 of 112
THEORY OF OPERATION
TW CLAMP
AND
HISTORY
PROG.
DIGITAL
LOOP
FILTER
TDC/PFD
÷R
÷S
DIGITAL PLL CORE
HOLDOVER
LOGIC
CONTROL
LOGIC
LOW NOISE
CLOCK
MULTIPLIER
AMP
SYSCLK PORT
INPUT
REF
MONITOR
IRQ AND
STATUS
LOGIC
DIGITAL
INTERFACE
IRQ
SYSCLKN
SYSCLKP
CLKINN
CLKINP
M0 TO M7
REFA
REFAA
OUT0P
PHASE
CONTROLLER
DDS/DAC
AD9548
4 OR 8
OUT0N
OUT_RSET
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
POST
DIV
POST
DIV
POST
DIV
POST
DIV
CLOCK
DISTRIBUTION
REFB
REFBB
REFC
REFCC
REFD
REFDD
DIFFERENTIAL
OR
SINGLE-ENDED
EXTERNAL
ANALOG
FILTER
08
02
2-
0
09
Figure 34. Detailed Block Diagram
OVERVIEW
The AD9548 provides clocking outputs directly related in phase
and frequency to the selected (active) reference but with jitter
characteristics primarily governed by the system clock. The
AD9548 supports up to eight reference inputs and a wide range
of reference frequencies. The core of this product is a digital
phase-locked loop (DPLL). The DPLL has a programmable
digital loop filter that greatly reduces jitter transferred from the
active reference to the output. The AD9548 supports both
manual and automatic holdover. While in holdover, the
AD9548 continues to provide an output as long as the DAC
sample clock is present. The holdover output frequency is a
time average of the output frequency history just prior to the
transition to the holdover condition.
The device offers manual and automatic reference switchover
capability if the active reference is degraded or fails completely.
A direct digital synthesizer (DDS) and integrated DAC consti-
tute a digitally controlled oscillator (DCO). The DCO output is
a sinusoidal signal (450 MHz maximum) at a frequency deter-
mined by the active reference frequency and the programmed
values of the reference prescaler (R) and feedback divider (S).
Although not explicitly shown in Figure 34, the S-divider has
both an integer and fractional component, which is similar to a
fractional-N synthesizer.
The SYSCLKx input provides the sample clock for the DAC,
which is either a directly applied high frequency source or a low
frequency source coupled with the integrated PLL-based
frequency multiplier. The low frequency option also allows for
the use of a crystal resonator connected directly across the
SYSCLKx inputs.
The DAC output routes directly off-chip, where an external
filter removes the sampling artifacts before returning the signal
on-chip at the CLKINx inputs. Once on-chip, an integrated
comparator converts the filtered sinusoidal signal to a clock
signal (square wave) with very fast rise and fall times.
The clock distribution section provides four output drivers.
Each driver is programmable either as a single differential
LVPECL/LVDS output or as a dual single-ended CMOS output.
Furthermore, each of the four outputs has a dedicated 30-bit
programmable postdivider. The clock distribution section
operates at up to 725 MHz. This enables use of a band-pass
reconstruction filter (for example, a SAW filter) to extract a
Nyquist image from the DAC output spectrum, thereby
allowing output frequencies that exceed the typical 450 MHz
limit at the DAC output.
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| AD9548XCPZ | 制造商:Analog Devices 功能描述: |
| AD9549 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Input Network Clock Generator/Synchronizer |
| AD9549/PCBZ | 制造商:Analog Devices 功能描述:DUAL INPUT NETWORK CLOCK GEN/SYNCHRONIZER - Bulk |
| AD9549A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9549A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9549ABCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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