參數(shù)資料
型號(hào): AD9557BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 49/92頁
文件大?。?/td> 0K
描述: IC CLOCK TRANSLATOR 40LFCSP
產(chǎn)品變化通告: Minor Mask Change 11/Apr/2012
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率轉(zhuǎn)換器
PLL:
主要目的: 以太網(wǎng),SONET/SDH
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,HSTL,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.25GHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-VQ(6x6)
包裝: 托盤
Data Sheet
AD9557
Rev. B | Page 53 of 92
POWER SUPPLY PARTITIONS
The AD9557 power supplies are divided into four groups:
DVDD3, DVDD, AVDD3, and AVDD. All power and ground
pins should be connected, even if certain blocks of the chip
are powered down.
RECOMMENDED CONFIGURATION FOR 3.3 V
SWITCHING SUPPLY
A popular power supply arrangement is to power the AD9557
with the output of a 3.3 V switching power supply.
When the AD9557 is powered using 3.3 V switching power
supplies, all of the 3.3 V supplies can be connected to the
3.3 V switcher output, and a 0.1 F bypass capacitor should
be placed adjacent to each 3.3 V power supply pin.
CONFIGURATION FOR 1.8 V SUPPLY
When 1.8 V supplies are preferred, it is recommended that
an LDO regulator, such as the ADP222, be used to generate
the 1.8 V supply from the 3.3 V supply.
The ADP222 offers excellent power supply rejection in
a small (2 mm × 2 mm) package. It has two 1.8 V outputs.
One output can be used for the DVDD pins (Pin 6, Pin 34,
and Pin 35), and the other output can drive the AVDD pins.
The ADP7104 is another good choice for converting 3.3 V to
1.8 V. The close-in noise of the ADP7104 is lower than that of
the ADP222; therefore, it may be better suited for applications
where close-in phase noise is critical and the AD9557 DPLL loop
bandwidth is <50 Hz. In such cases, all 1.8 V supplies can be
connected to one ADP7104.
Use of Ferrite Beads on 1.8 V Supplies
To ensure the very best output-to-output isolation, one ferrite
bead should be used instead of a bypass capacitor for each of
the following AVDD pins: Pin 11, Pin 17, and Pin 18. The ferrite
beads should be placed in between the 1.8 V LDO output and
each pin listed above. Ferrite beads that have low (<0.7 ) dc
resistance and approximately 600 impedance at 100 MHz are
suitable for this application.
See Table 2 for the current consumed by each group. Refer to
Figure 20, Figure 21, and Figure 22 for information on the
power consumption vs. output frequency.
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