參數(shù)資料
型號(hào): AD9557BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 69/92頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK TRANSLATOR 40LFCSP
產(chǎn)品變化通告: Minor Mask Change 11/Apr/2012
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 時(shí)鐘/頻率轉(zhuǎn)換器
PLL:
主要目的: 以太網(wǎng),SONET/SDH
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,HSTL,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.25GHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-VQ(6x6)
包裝: 托盤(pán)
Data Sheet
AD9557
Rev. B | Page 71 of 92
Table 60. History Accumulation Timer
Address
Bits
Bit Name
Description
0x0314
[7:0]
History accumulation timer (ms)
History accumulation timer bits[7:0].
Default: 0x0A. For Register 0x0314 and Register 0x0315, 0x000A = 10 ms.
Maximum is 65 sec. This register controls the amount of tuning word averaging used to
determine the tuning word used in holdover. Never program a timer value of zero.
The default value is 0x000A = 10 decimal, which equates to 10 ms.
0x0315
[7:0]
History accumulation timer bits[15:8].
Default: 0x00.
Table 61. History Mode
Address
Bits
Bit Name
Description
0x0316
[7:5]
Reserved
Reserved.
4
Single sample fallback
Controls holdover history. If tuning word history is not available for the reference
that was active just prior to holdover, then:
0 (default) = uses the free run frequency tuning word register value.
1 = uses the last tuning word from the DPLL.
3
Persistent history
Controls holdover history initialization. When switching to a new reference:
0 (default) = clear the tuning word history.
1 = retain the previous tuning word history.
[2:0]
Incremental average
History mode value from 0 to 7 (default: 0).
When set to non-zero, causes the first history accumulation to update prior to the
first complete averaging period. After the first full interval, updates occur only at the
full period.
0 (default) = update only after the full interval has elapsed.
1 = update at 1/2 the full interval.
2 = update at 1/4 and 1/2 of the full interval.
3 = update at 1/8, 1/4, and 1/2 of the full interval.
...
7 = update at 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, and 1/2 of the full interval.
Table 62. Base Digital Loop Filter with High Phase Margin (PM = 88.5°, BW = 0.1 Hz, Third Pole Frequency = 10 Hz, N1 = 1)1
Address
Bits
Bit Name
Description
0x0317
[7:0]
HPM Alpha-0 linear
Alpha-0 coefficient linear bits[7:0].
Default: 0x8C
0x0318
[7:0]
Alpha-0 coefficient linear bits[15:8]
0x0319
7
Reserved
[6:0]
HPM Alpha-1 exponent
Alpha-1 coefficient exponent bits[6:0]
0x031A
[7:0]
HPM Beta-0 linear
Beta-0 coefficient linear bits[7:0]
0x031B
[7:0]
Beta-0 coefficient linear bits[15:8]
0x031C
7
Reserved
[6:0]
HPM Beta-1 exponent
Beta-1 coefficient exponent bits[6:0]
0x031D
[7:0]
HPM Gamma-0 linear
Gamma-0 coefficient linear bits[7:0]
0x031E
[7:0]
Gamma-0 coefficient linear bits[15:8]
0x031F
7
Reserved
[6:0]
HPM Gamma-1 exponent
Gamma-1 coefficient exponent bits[6:0]
0x0320
[7:0]
HPM Delta-0 linear
Delta-0 coefficient linear bits[7:0]
0x0321
[7:0]
Delta-0 coefficient linear bits[15:8]
0x0322
7
Reserved
[6:0]
HPM Delta-1 exponent
Delta-1 coefficient exponent bits[6:0]
1
Note that the base digital loop filter coefficients (α, β, γ, and δ) have the following general form: x(2y), where x is the linear component and y is the exponential
component of the coefficient. The value of the linear component (x) constitutes a fraction, where 0 ≤ x ≤ 1. The exponential component (y) is a signed integer.
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