參數(shù)資料
型號(hào): AD9557BCPZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 9/92頁(yè)
文件大小: 0K
描述: IC CLOCK TRANSLATOR 40LFCSP
產(chǎn)品變化通告: Minor Mask Change 11/Apr/2012
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率轉(zhuǎn)換器
PLL:
主要目的: 以太網(wǎng),SONET/SDH
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,HSTL,LVDS
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.25GHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-VQ(6x6)
包裝: 托盤
Data Sheet
AD9557
Rev. B | Page 17 of 92
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS).
1
IRQ
2
SCLK/SCL
3
SDIO/SDA
4
SDO
5
CS
6
DVDD
7
AVDD
8
XOA
9
XOB
10
AVDD
23 AVDD
24 AVDD
25 RESET
26 PINCONTROL
27 SYNC
28 REFA
29 REFA
30 DVDD3
22 AVDD
21 LF_VCO2
1
A
V
DD
12
OU
T1
13
OU
T1
15
OU
T0
17
A
V
DD
16
OU
T0
18
A
V
DD
19
A
V
DD3
20
L
DO
_V
CO
2
14
A
V
DD3
33
RE
F
B
34
DV
DD
35
DV
DD
36
M0
37
M1
38
M2
39
M3
40
DV
DD3
32
RE
F
B
31
DV
DD3
TOP VIEW
(Not to Scale)
AD9557
09197-
002
Figure 2. Pin Configuration
Table 20. Pin Function Descriptions
Pin No.
Mnemonic
Input/
Output
Pin Type
Description
1
IRQ
O
3.3 V CMOS
Interrupt Request Line.
2
SCLK/SCL
I
3.3 V CMOS
Serial Programming Clock (SCLK) in SPI Mode. Data clock for serial programming.
Serial Clock Pin (SCL) in I2C Mode.
3
SDIO/SDA
I/O
3.3 V CMOS
Serial Data Input/Output (SDIO) in SPI Mode. When the device is in 4-wire SPI
mode, data is written via this pin. In 3-wire mode, both data reads and writes
occur on this pin. There is no internal pull-up/pull-down resistor on this pin.
Serial Data Pin (SDA) in I2C Mode.
4
SDO
O
3.3 V CMOS
Serial Data Output. Use this pin to read data in 4-wire mode. There is no internal
pull-up/pull-down resistor on this pin. This pin is high impedance in the default
3-wire mode.
5
A
CSE
I
3.3 V CMOS
Chip Select (SPI), Active Low. When programming a device, this pin must be held
low. In systems where more than one AD9557 is present, this pin enables
individual programming of each AD9557. This pin has an internal 10 k pull-up
resistor.
6, 34, 35
DVDD
I
Power
1.8 V Digital Supply.
7, 10, 22,
23, 24
AVDD
I
Power
1.8 V Analog Power Supply.
8
XOA
I
Differential
input
System Clock Input. XOA contains internal dc biasing and should be ac-coupled
with a 0.01 μF capacitor, except when using a crystal, in which case connect the
crystal across XOA and XOB. Single-ended 1.8 V CMOS is also an option but can
introduce a spur if the duty cycle is not 50%. When using XOA as a single-ended
input, connect a 0.01 μF capacitor from XOB to ground.
9
XOB
I
Differential
input
Complementary System Clock Input. Complementary signal to XOA. XOB contains
internal dc biasing and should be ac-coupled with a 0.01 μF capacitor, except
when using a crystal, in which case connect the crystal across XOA and XOB.
11, 17, 18
AVDD
I
Power
1.8 V Analog (Output Divider and Drivers) Power Supply.
12
A
OUT1E
O
HSTL, LVDS, or
1.8 V CMOS
Complementary Output 1. This output can be configured as HSTL, LVDS, or
single-ended 1.8 V CMOS.
13
OUT1
O
HSTL, LVDS, or
1.8 V CMOS
Output 1. This output can be configured as HSTL, LVDS, or single-ended 1.8 V CMOS.
LVPECL levels can be achieved by ac coupling and using the Thevenin-equivalent
termination as described in the Input/Output Termination Recommendations
section.
14, 19
AVDD3
I
Power
3.3 V Analog Power Supply.
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