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參數(shù)資料
| 型號： | AD9557BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 85/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK TRANSLATOR 40LFCSP |
| 產(chǎn)品變化通告： | Minor Mask Change 11/Apr/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率轉(zhuǎn)換器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，HSTL，LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
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AD9557
Data Sheet
Rev. B | Page 86 of 92
Table 109. Digital PLL Lock Detect Tub Levels
Address
Bits
Bit Name
Description
0x0D11
[7:0]
Phase tub
Read-only digital PLL lock detect bathtub level[7:0] (see the DPLL Frequency Lock Detector section).
0x0D12
[7:4]
Reserved.
[3:0]
Read-only digital PLL lock detect bathtub level[11:8] (see the DPLL Frequency Lock Detector section).
0x0D13
[7:0]
Frequency tub
Read-only digital PLL lock detect bathtub level[7:0] (see the DPLL Phase Lock Detector section).
0x0D14
[7:4]
Reserved
Reserved.
[3:0]
Frequency tub
Read-only digital PLL lock detect bathtub level[11:8] (see the DPLL Phase Lock Detector section).
EEPROM CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E3C)
Table 110. EEPROM Control
Address
Bits
Bit Name
Description
0x0E00
[7:1]
Reserved
Reserved.
0
Write enable
EEPROM write enable/protect.
0 (default) = EEPROM write protected
1 = EEPROM write enabled.
0x0E01
[7:4]
Reserved
Reserved.
[3:0]
Conditional value
When set to a non-zero value, establishes the condition for EEPROM downloads. Default: 0.
0x0E02
[7:1]
Reserved
Reserved.
0
Save to EEPROM
Uploads data to the EEPROM (see the EEPROM Storage Sequence (Register 0X0E10 to Register
0X0E3C) section).
0x0E03
[7:2]
Reserved
Reserved.
1
Load from EPROM
Downloads data from the EEPROM.
0
Reserved
Reserved.
EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3C)
The default settings of Register 0x0E10 to Register 0x0E3C contain the default EEPROM instruction sequence. The tables in this section
provide descriptions of the register defaults, assuming that the controller has been instructed to carry out an EEPROM storage sequence
in which all of the registers are stored and loaded by the EEPROM.
Table 111. EEPROM Storage Sequence for System Clock Settings
Address
Bits
Bit Name
Description
0x0E10
[7:0]
EEPROM ID
The default value of this register is 0x01, which the controller interprets as a data instruction. Its
decimal value is 1, so this tells the controller to transfer two bytes of data (1 + 1), beginning at the
address specified by the next two bytes. The controller stores 0x01 in the EEPROM and increments
the EEPROM address pointer.
0x0E11
[7:0]
The default value of these two registers is 0x0006. Note that Register 0x0E11 and Register 0x0E12
are the most significant and least significant bytes of the target address, respectively. Because the
previous register contains a data instruction, these two registers define a starting address (in this
case, 0x0006). The controller stores 0x0006 in the EEPROM and increments the EEPROM pointer by 2.
It then transfers two bytes from the register map (beginning at Address 0x0006) to the EEPROM
and increments the EEPROM address pointer by 3 (two data bytes and one checksum byte). The
two bytes transferred correspond to the system clock parameters in the register map.
0x0E12
[7:0]
0x0E13
[7:0]
System clock
The default value of this register is 0x08, which the controller interprets as a data instruction. Its
decimal value is 8, so this tells the controller to transfer nine bytes of data (8 + 1), beginning at the
address specified by the next two bytes. The controller stores 0x08 in the EEPROM and increments
the EEPROM address pointer.
0x0E14
[7:0]
The default value of these two registers is 0x0100. Note that Register 0x0E14 and Register 0x0E15
are the most significant and least significant bytes of the target address, respectively. Because the
previous register contains a data instruction, these two registers define a starting address (in this
case, 0x0100). The controller stores 0x0100 in the EEPROM and increments the EEPROM pointer by 2.
It then transfers nine bytes from the register map (beginning at Address 0x0100) to the EEPROM
and increments the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The
nine bytes transferred correspond to the system clock parameters in the register map.
0x0E15
[7:0]
0x0E16
[7:0]
I/O update
The default value of this register is 0x80, which the controller interprets as an I/O update instruction.
The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
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| AD9557BCPZ-REEL7 | 功能描述:IC CLK XLATR PLL 1250MHZ 40LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
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