參數(shù)資料
型號(hào): AD9628BCPZRL7-105
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 23/44頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 105MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 12
采樣率(每秒): 105M
數(shù)據(jù)接口: LVDS,并聯(lián),串行,SPI
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類(lèi)型: 4 個(gè)單端,2 個(gè)差分
AD9628
Rev. 0 | Page 3 of 44
GENERAL DESCRIPTION
The AD9628 is a monolithic, dual-channel, 1.8 V supply, 12-bit,
125 MSPS/105 MSPS analog-to-digital converter (ADC). It
features a high performance sample-and-hold circuit and on-
chip voltage reference.
The product uses multistage differential pipeline architecture
with output error correction logic to provide 12-bit accuracy at
125 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.
The digital output data is presented in offset binary, Gray code, or
twos complement format. A data output clock (DCO) is provided
for each ADC channel to ensure proper latch timing with receiving
logic. 1.8 V CMOS or LVDS output logic levels are supported.
Output data can also be multiplexed onto a single output bus.
The AD9628 is available in a 64-lead RoHS-compliant LFCSP and
is specified over the industrial temperature range (40°C to
+85°C). This product is protected by a U.S. patent.
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