- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10094 > AD9628BCPZRL7-105 (Analog Devices Inc)IC ADC 12BIT 105MSPS 64LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9628BCPZRL7-105 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 105MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 105M |
| 數(shù)據(jù)接口： | LVDS，并聯(lián)，串行，SPI |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，2 個差分 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD9628
Rev. 0 | Page 30 of 44
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNRLF) at a given input frequency (fINPUT) due to
jitter (tJRMS) can be calculated by
SNRHF = 10 log[(2π × fINPUT × tJRMS)2 + 10
)
10
/
(
LF
SNR
]
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 59.
80
75
70
65
60
55
50
45
1
10
100
1k
FREQUENCY (MHz)
S
NR
(d
B
F
S)
0.5ps
0.2ps
0.05ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
09976-
064
Figure 59. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9628.
To avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal-controlled oscillators make the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
See the AN-501 Application Note and the AN-756 Application
Note available on www.analog.com for more information.
CHANNEL/CHIP SYNCHRONIZATION
The AD9628 has a SYNC input that offers the user flexible
synchronization options for synchronizing sample clocks
across multiple ADCs. The input clock divider can be enabled
to synchronize on a single occurrence of the SYNC signal or on
every occurrence. The SYNC input is internally synchronized
to the sample clock; however, to ensure that there is no timing
uncertainty between multiple parts, the SYNC input signal should
be externally synchronized to the input clock signal, meeting the
setup and hold times shown in Table 5. Drive the SYNC input
using a single-ended CMOS-type signal.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 60, the analog core power dissipated by
the AD9628 is proportional to its sample rate. The digital
power dissipation of the CMOS outputs are determined
primarily by the strength of the digital drivers and the load
on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (26, in the case of the
AD9628).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is estab-
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 60 was
taken in CMOS mode using the same operating conditions as those
used for the power supplies and power consumption specifications
in Table 1 with a 5 pF load on each output driver.
100
40
90
140
190
240
5
25
45
65
85
105
125
PO
W
ER
(m
W
)
SU
PP
L
Y
CURRE
NT
(
mA)
ENCODE RATE (MSPS)
IAVDD
IDRVDD
TOTAL POWER
09976-
105
0
10
20
30
40
50
60
70
80
90
Figure 60. AD9628-125 Power and Current vs. Clock Rate (1.8 V CMOS
Output Mode)
40
60
80
100
120
140
160
180
200
0
10
20
30
40
50
60
70
80
90
5
25
45
65
85
105
PO
W
ER
(m
W
)
SU
PP
L
Y
CURRE
NT
(
mA)
ENCODE RATE (MSPS)
IAVDD
IDRVDD
TOTAL POWER
09976-
101
Figure 61. AD9648-105 Power and Current vs. Clock Rate (1.8 V CMOS
Output Mode)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-2NY-IU-F3 | CONVERTER MOD DC/DC 3.3V 132W |
| VI-23R-IW-F4 | CONVERTER MOD DC/DC 7.5V 100W |
| LT1537CG#TRPBF | IC TXRX 5V RS232 LOW-PWR 28-SSOP |
| IDT72231L25JI8 | IC FIFO SYNC 512X9 25NS 32PLCC |
| EXP-0931/07/S | CONN JAM NUT 7POS IP68 W/SOCKETS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9628BCPZRL7-125 | 功能描述:IC ADC 12BIT 125MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD9629 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS 1.8 V Analog-to-Digital Converter |
| AD9629-20EBZ | 功能描述:BOARD EVALUATION AD9629 20MSPS RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| AD9629-20EBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter |
| AD9629-40EBZ | 功能描述:BOARD EVALUATION AD9629 40MSPS RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。