參數(shù)資料
型號(hào): AD9628BCPZRL7-105
廠商: Analog Devices Inc
文件頁(yè)數(shù): 5/44頁(yè)
文件大?。?/td> 0K
描述: IC ADC 12BIT 105MSPS 64LFCSP
標(biāo)準(zhǔn)包裝: 750
位數(shù): 12
采樣率(每秒): 105M
數(shù)據(jù)接口: LVDS,并聯(lián),串行,SPI
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個(gè)單端,2 個(gè)差分
AD9628
Rev. 0 | Page 13 of 44
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D8B
D9B
D
R
V
DD
D10B
D
1
1B
(
M
S
B)
O
RB
DCO
B
DCO
A
NC
D
R
V
DD
NC
D0
A
(L
SB
)
D1
A
D2
A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
A
V
DD
A
V
DD
V
IN+
B
V
IN–B
A
V
DD
A
V
DD
RBI
AS
V
CM
SEN
SE
VR
EF
A
V
DD
A
V
DD
V
IN–
A
V
IN+
A
V
DD
A
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK+
CLK–
SYNC
NC
D0B (LSB)
D1B
DRVDD
D2B
D3B
D4B
D5B
D6B
D7B
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
ORA
D11A (MSB)
D10A
D9A
D8A
D7A
DRVDD
D6A
D5A
D4A
D3A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9628
PARALLEL CMOS
TOP VIEW
(Not to Scale)
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
09976-
006
Figure 6. Parallel CMOS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
10, 19, 28, 37
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54,
59, 60, 63, 64
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
4, 5, 6, 7, 25, 26,
27, 29
NC
No Connect. Do not connect to these pins.
0
AGND,
Exposed Pad
Ground
The exposed thermal pad on the bottom of the package provides the analog
ground for the part. This exposed pad must be connected to ground for proper
operation.
ADC Analog
51
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
52
VINA
Input
Differential Analog Input Pin () for Channel A.
62
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
61
VINB
Input
Differential Analog Input Pin () for Channel B.
55
VREF
Input/Output
Voltage Reference Input/Output.
56
SENSE
Input
Reference Mode Selection.
58
RBIAS
Input/Output
External Reference Bias Resistor.
57
VCM
Output
Common-Mode Level Bias Output for Analog Inputs.
1
CLK+
Input
ADC Clock Input—True.
2
CLK
Input
ADC Clock Input—Complement.
Digital Input
3
SYNC
Input
Digital Synchronization Pin. Slave mode only.
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