參數(shù)資料
型號(hào)： AD9628BCPZRL7-105
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 25/44頁(yè)
文件大小： 0K
描述： IC ADC 12BIT 105MSPS 64LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 105M
數(shù)據(jù)接口： LVDS，并聯(lián)，串行，SPI
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 4 個(gè)單端，2 個(gè)差分
AD9628
Rev. 0 | Page 31 of 44
The AD9628 is placed in power-down mode either by the SPI
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates less than 2 mW. During power-down, the
output drivers are placed in a high impedance state. Asserting
the PDWN pin low returns the AD9628 to its normal operating
mode. Note that PDWN is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI, the user can place the ADC in power-
down mode or standby mode. Standby mode allows the user to
keep the internal reference circuitry powered when faster wake-
up times are required. See the Memory Map section for more
details.
DIGITAL OUTPUTS
The AD9628 output drivers can be configured to interface with
either 1.8 V CMOS or 1.8 V LVDS logic families. The default
output mode is CMOS, with each channel output on separate
busses as shown in Figure 2.
In CMOS output mode, the CMOS output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies and may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The CMOS output can also be configured for interleaved CMOS
output mode via the SPI port. In interleaved CMOS mode, the data
for both channels is output onto a single output bus to reduce the
total number of traces required. The timing diagram for interleaved
CMOS output mode is shown in Figure 3.
The interleaved CMOS output mode is enabled globally onto
both output channels via Bit 5 in Register 0x14. The unused
channel output can be disabled by selecting the appropriate bit
(Bit 1 or Bit 0) in Register 0x05 and then writing a 1 to the local
(channel-specific) output port disable bit (Bit 4) in Register 0x14.
The output data format can be selected to be either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 13).
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or Gray code when using the SPI control.
Table 13. SCLK/DFS Mode Selection (External Pin Mode)
Voltage at Pin
SCLK/DFS
SDIO/DCS
AGND
Offset binary (default)
DCS disabled
DRVDD
Twos complement
DCS enabled (default)
Digital Output Enable Function (OEB)
The AD9628 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled through the SPI
interface and can subsequently be controlled using the OEB
pin or through the SPI. Once enabled via the SPI (Bit 7) in
Register 0x101, and the OEB pin is low, the output data drivers
and DCOs are enabled. If the OEB pin is high, the output data
drivers and DCOs are placed in a high impedance state. This
OEB function is not intended for rapid access to the data bus.
Note that OEB is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
When using the SPI interface, the data outputs and DCO of
each channel can be independently three-stated by using the
output port disable bit (Bit 4) in Register 0x14.
TIMING
The AD9628 provides latched data with a pipeline delay of
16 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9628. These
transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9628 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9628 provides two data clock output (DCO) signals
intended for capturing the data in an external register. In CMOS
output mode, the data outputs are valid on the rising edge of DCO,
unless the DCO clock polarity has been changed via the SPI. In
LVDS output mode, the DCO and data output switching edges
are closely aligned. Additional delay can be added to the DCO
output using SPI Register 0x17 to increase the data setup time.
In this case, the Channel A output data is valid on the rising
edge of DCO, and the Channel B output data is valid on the
falling edge of DCO. See Figure 2, Figure 3, and Figure 4 for
a graphical timing description of the output modes.
Table 14. Output Data Format
Input (V)
Condition (V)
Offset Binary Output Mode
Twos Complement Mode
OR
VIN+ VIN
< VREF 0.5 LSB
0000 0000 0000
1000 0000 0000
1
VIN+ VIN
= VREF
0000 0000 0000
1000 0000 0000
0
VIN+ VIN
= 0
1000 0000 0000
0000 0000 0000
0
VIN+ VIN
= +VREF 1.0 LSB
1111 1111 1111
0111 1111 1111
0
VIN+ VIN
> +VREF 0.5 LSB
1111 1111 1111
0111 1111 1111
1
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