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參數資料
| 型號： | AD9629BCPZRL7-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 15/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 80MSPS 32LFCSP |
| 標準包裝： | 1,500 |
| 位數： | 12 |
| 采樣率（每秒）： | 80M |
| 數據接口： | 串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 2 個單端，單極；1 個差分，單極 |
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AD9629
Rev. 0 | Page 22 of 32
In SPI mode, the AD9629 can be placed in power-down mode
directly via the SPI port, or by using the programmable external
MODE pin. In non-SPI mode, power-down is achieved by
asserting the PDWN pin high. In this state, the ADC typically
dissipates 500 μW. During power-down, the output drivers are
placed in a high impedance state. Asserting PDWN low (or the
MODE pin in SPI mode) returns the AD9629 to its normal
operating mode. Note that PDWN is referenced to the digital
output driver supply (DRVDD) and should not exceed that
supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details.
DIGITAL OUTPUTS
The AD9629 output drivers can be configured to interface with
1.8 V to 3.3 V CMOS logic families. Output data can also be
multiplexed onto a single output bus to reduce the total number
of traces required.
The CMOS output drivers are sized to provide sufficient output
current to drive a wide variety of logic families. However, large
drive currents tend to cause current glitches on the supplies and
may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
The output data format can be selected to be either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 11).
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
Table 11. SCLK/DFS and SDIO/PDWN Mode Selection
(External Pin Mode)
Voltage at Pin
SCLK/DFS
SDIO/PDWN
AGND
Offset binary (default)
Normal operation
(default)
DRVDD
Twos complement
Outputs disabled
Digital Output Enable Function (OEB)
When using the SPI interface, the data outputs and DCO can be
independently three-stated by using the programmable external
MODE pin. The MODE pin (OEB) function is enabled via
Bits[6:5] of Register 0x08.
If the MODE pin is configured to operate in traditional OEB
mode and the OEB pin is low, the output data drivers and
DCOs are enabled. If the OEB pin is high, the output data
drivers and DCOs are placed in a high impedance state. This
OEB function is not intended for rapid access to the data bus.
Note that OEB is referenced to the digital output driver supply
(DRVDD) and should not exceed that supply voltage.
TIMING
The AD9629 provides latched data with a pipeline delay of
9 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9629. These
transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9629 is 3 MSPS. At
clock rates below 3 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9629 provides a data clock output (DCO) signal
intended for capturing the data in an external register. The CMOS
data outputs are valid on the rising edge of DCO, unless the DCO
clock polarity has been changed via the SPI. See Figure 2 for a
graphical timing description.
Table 12. Output Data Format
Input (V)
Condition (V)
Offset Binary Output Mode
Twos Complement Mode
OR
VIN+ VIN
< VREF 0.5 LSB
0000 0000 0000
1000 0000 0000
1
VIN+ VIN
= VREF
0000 0000 0000
1000 0000 0000
0
VIN+ VIN
= 0
1000 0000 0000
0000 0000 0000
0
VIN+ VIN
= +VREF 1.0 LSB
1111 1111 1111
0111 1111 1111
0
VIN+ VIN
> +VREF 0.5 LSB
1111 1111 1111
0111 1111 1111
1
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