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| 型號： | AD9637-80EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9637 |
| 標準包裝： | 1 |
| 系列： | * |
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AD9637
Data Sheet
Rev. A | Page 36 of 40
APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting the design and layout of the AD9637 as a system,
it is recommended that the designer become familiar with these
guidelines, which describes the special circuit connections and
layout requirements that are needed for certain pins.
POWER AND GROUND RECOMMENDATIONS
When connecting power to the AD9637, it is recommended
that two separate 1.8 V supplies be used. Use one supply for
analog (AVDD); use a separate supply for the digital outputs
(DRVDD). For both AVDD and DRVDD, several different
decoupling capacitors should be used to cover both high and
low frequencies. Place these capacitors close to the point of
entry at the PCB level and close to the pins of the part, with
minimal trace length.
A single PCB ground plane should be sufficient when using the
AD9637. With proper decoupling and smart partitioning of the
PCB analog, digital, and clock sections, optimum performance
is easily achieved.
CLOCK STABILITY CONSIDERATIONS
When powered on, the AD9637 goes into an initialization phase
where an internal state machine sets up the biases and the
registers for proper operation. During the initialization process,
the AD9637 needs a stable clock. If the ADC clock source is not
present or not stable during ADC power-up, it will disrupt the
state machine and cause the ADC to start up in an unknown
state. To correct this, an initialization sequence needs to be
re-invoked after the ADC clock is stable. This is done by issuing
a digital reset via Register 0x08. In the default configuration
(internal VREF, ac-coupled input) where VREF and VCM are
supplied by the ADC itself, a stable clock during power-up is
sufficient. In the case where VREF and/or VCM are supplied by
an external source, these too should be stable at power up;
otherwise, a subsequent digital reset via Register 0x08 will
be needed. The pseudo-code sequence for a digital reset is
as follows:
SPI_Write (0x08, 0x03); # Digital Reset
SPI_Write (0x08, 0x00); # Normal Operation
EXPOSED PAD THERMAL HEAT SLUG
RECOMMENDATIONS
It is required that the exposed pad on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9637. An
exposed continuous copper plane on the PCB should mate to
the AD9637 exposed pad, Pin 0. The copper plane should have
several vias to achieve the lowest possible resistive thermal path
for heat dissipation to flow through the bottom of the PCB.
These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a silk-
screen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
guarantees only one tie point. For detailed information on
packaging and the PCB layout of chip scale packages, see the
AN-772 Application Note, A Design and Manufacturing Guide
for the Lead Frame Chip Scale Package (LFCSP), at
VCM
The VCM pin should be decoupled to ground with a 0.1 μF
capacitor.
REFERENCE DECOUPLING
The VREF pin should be externally decoupled to ground with
a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF
ceramic capacitor.
SPI PORT
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9637 to keep these signals from transitioning at the con-
verter inputs during critical sampling periods.
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