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參數(shù)資料
| 型號： | AD9641-155KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR AD9641 |
| 設(shè)計(jì)資源： | AD9641 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9641
Rev. B | Page 25 of 36
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9641 includes built-in test features designed to enable
verification of the integrity of the channel as well as facilitate
board level debugging. A BIST (built-in self-test) feature is included
that verifies the integrity of the digital datapath of the AD9641.
Various output test options are also provided to place predictable
values on the outputs of the AD9641.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9641 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs
for 512 cycles and stops. The BIST signature value is placed in
Register 0x24 and Register 0x25. The outputs are not disconnected
during this test; therefore, the PN sequence can be observed as
it runs. The PN sequence can be continued from its last value or
reset from the beginning, based on the value programmed in
Register 0x0E, Bit 2. The BIST signature result varies based on
the channel configuration.
OUTPUT TEST MODES
Digital test patterns can be inserted at various points along the
signal path within the AD9641 as shown in Figure 69. The ability
to inject these signals at several locations facilitates debugging
of the JESD204A serial communication link.
Register 0x0D allows test signals generated at the output of the
ADC core to be fed directly into the input of the serial link. The
output test options available from Register 0x0D are shown in
Table 14. When an output test mode is enabled, the analog
section of the ADC is disconnected from the digital back end
blocks and the test pattern is run through the output formatting
block. Some of the test patterns are subject to output formatting,
and some are not. The seed value for the PN sequence tests can be
forced if the PN reset bits are used to hold the generator in reset
mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can
be performed with or without an analog signal (if present, the
analog signal is ignored), but they do require an encode clock.
For more information, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
ADC TEST PATTERNS
14-BIT
SPI REGISTER 0x0D
BITS [3:0] ≠ 0000
JESD204A
SAMPLE
CONSTRUCTION
JESD204A TEST PATTERNS
16-BIT
SPI REGISTER 0x62 BITS [5:4] =
00 AND BITS [2:0] ≠ 000
JESD204A TEST PATTERNS
10-BIT
SPI REGISTER 0x62 BITS [5:4] =
01 AND BITS [2:0] ≠ 000
FRAME
CONSTRUCTION
SCRAMBLER
(OPTIONAL)
8-BIT/10-BIT
ENCODER
FRAMER
SERIALIZER
OUTPUT
TAIL BITS
ADC CORE
09
21
0-
05
1
Figure 69. Block Diagram Showing Digital Test Modes
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