參數(shù)資料
型號(hào)： AD9641-155KITZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/36頁(yè)
文件大?。?/td> 0K
描述： KIT EVAL FOR AD9641
設(shè)計(jì)資源： AD9641 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： *
Data Sheet
AD9641
Rev. B | Page 29 of 36
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into four sections: the chip
configuration registers (Address 0x00 to Address 0x02); the transfer
register (Address 0xFF); the ADC functions registers, including
setup, control, and test (Address 0x08 to Address 0x3A); and the
JESD204A configuration registers (Address 0x60 to Address 0x78).
The memory map register table (see Table 17) lists the default
hexadecimal value for each hexadecimal address shown. The
column with the heading Bit 7 (MSB) is the start of the default
hexadecimal value given. For example, Address 0x18, the input
span select register, has a hexadecimal default value of 0x00. This
means that Bit 0 through Bit 4 = 0, and the remaining bits are 0s.
This setting is the default reference selection setting. The default
value uses a 1.75 V p-p reference. For more information on this
function and others, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI. This application note details the
functions controlled by Register 0x00 to Register 0xFF.
Open Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
Default Values
After the AD9641 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 17.
Logic Levels
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 through Address 0x78 are shadowed. Writes to the
addresses do not affect part operation until a transfer command is
issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simulta-
neously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and the bit autoclears.
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
Chip Configuration Registers
0x00
SPI port
configuration
0
LSB first
Soft reset
1
Soft reset
LSB first
0
0x18
Nibbles are
mirrored so
LSB- or MSB-
first mode
registers
correctly,
regardless of
shift mode
0x01
Chip ID
8-bit chip ID[7:0]
(default)
0x80
Read only
0x02
Chip grade
Open
Speed grade ID
00 = 80 MSPS
10 = 155 MSPS
Open
Speed grade
ID used to
differentiate
devices;
read only
Transfer Register
0xFF
Transfer
Open
Transfer
0x00
Synchronous
transfer of
data from
the master
shift register
to the slave
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