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參數(shù)資料
| 型號(hào)： | AD9641-155KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 26/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR AD9641 |
| 設(shè)計(jì)資源： | AD9641 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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AD9641
Data Sheet
Rev. B | Page 32 of 36
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x6F
JESD204A
number of
octets per
frame (F)
JESD204A number of octets per frame (F)
(bits are calculated based on the equation F = (M × 2)/L)
0x01
Read only.
0x70
JESD204A
number of
frames per
multiframe
(K)
Open
JESD204A number of frames per multiframe (K)
0x0F
0x71
JESD204A
number of
converters
per link per
converter
device (link)
(M)
Open
Number of
converters
per link
per device
0 = link
connected to
one ADC
(M = 1)
1 = reserved
0x00
Read only.
0x72
JESD 204A
converter
resolution (N)
and control
bits per
sample (CS)
Number of control bits per
sample (CS)
00 = no control bits
(CS = 0)
01 = one control bit
(CS = 1)
10 = two control bits
(CS = 2)
11 = unused
Open
Converter resolution (N) (read only)
0x4D
0x73
JESD204A
total bits per
sample (N’)
Open
Total number of bits per sample (N’) (read only)
0x0F
Read only.
0x74
JESD204A
samples per
converter (S)
per frame
cycle
Open
Samples per converter per frame cycle (S) (read only)
(always 1 for the AD9641)
0x00
Read only.
0x75
JESD204A
HD and CF
configuration
Enable HD
(high
density)
format
Open
Number of control words per frame clock cycle per link (CF)
(always 0 for the AD9641 (read only))
0x00
0x76
JESD204A
Serial
Reserved
Field 1
(RES1)
Serial Reserved Field 1 (RES1)
(these registers are available for customer use)
0x00
0x77
JESD204A
Serial
Reserved
Field 2
(RES2)
Serial Reserved Field 2 (RES2)
(these registers are available for customer use)
0x00
0x78
JESD204A
checksum
value for
lane (FCHK)
Serial checksum value for lane (FCHK)
0x00
Read only
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0x25, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Sync Control (Address 0x3A)
Bits[7:3]—Open
Bit 2—Clock Divider Next Sync Only
If the master sync buffer enable bit (Address 0x3A, Bit 0) and
the clock divider sync enable bit (Address 0x3A, Bit 1) are high,
Bit 2 allows the clock divider to sync to the first sync pulse it
receives and to ignore the rest. The clock divider sync enable bit
(Address 0x3A, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal
is enabled when Bit 1 and Bit 0 are high. This is in continuous
sync mode.
Bit 0—Master Sync Buffer Enable
Bit 0 must be high to enable any of the sync functions. If the
sync capability is not used, this bit should remain low to
conserve power.
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